HDMI I2C does not work for some users

[abrasive]

Some people (eg. jorgegeorge on IRC) have reported issues with:

• HDMI audio not working
• HDMI video defaulting to fixed res (eg. 640x480 with newer kernels or 1280x720 with older)

jorgegeorge reported that the edid read as all zeroes. This seems to be an I2C issue causing both of these.

[HSTe]

Looks like others with same problem:
https://community.freescale.com/thread/305063

[abrasive]

That's a different issue - I fixed it here: 6ea2512#L1L1542

Essentially only CEA modes were permitted (ie. TV modes).

[abrasive]

This also can't be worked around using the video= kernel parameter, as it only selects from the modelist read from the monitor rather than setting a mode from scratch. Should probably add a ,force, parameter.

[HSTe]

hdmi audio works when setting video= resolution in boot.scr.
I tried setting 1080 and 720 resolution and audio worked.
When not setting resolution my screen default to a higher resolution and audio doesn't work

[abrasive]

I've had a poke at the DDC bus, and everything looks healthy at 100kHz.
The voltage on the monitor detect pin with my monitors is only 2.45V though, even though it should be pulled to 5 in the monitor - and that's close to the spec's threshold of 2.4. I've also had issues with certain video modes where the thing continuously rereads the EDID. So perhaps there is an overly small pulldown in the stick?

Workaround would be to force HDMI detection to on. Has anyone got a troublesome monitor or TV we can work with?

[abrasive]

hp__ tested this and found HDMI detection reports correctly.

[HSTe]

There is single method to set clock-rate for both audio and video pll-s
in i.MX6q clock system implementation. That's possible due to they have
similar set of registers with a different bases. But there is also one
common register: CCM_ANALOG_MISC2, which contains post-dividers.

From mailing list. Could this be sth for the video audio problem?

[meta-freescale] [PATCH] arm/mach-mx6: fix pll4 set_rate callback
Innboks
x
Alexander Smirnov alex.bluesman.smirnov@gmail.com via yoctoproject.org

1. mai (For 6 dager siden)

til meta-freescale

In current implementation, independently of whether audio or video clock
is going to be set, the mask 0xc0000000 is applied to MISC2 register.
This means, that if the audio clock rate is changed, the video clock
post-dividers possibly will be corrupted.

This patch fixes the issue described above.

Signed-off-by: Alexander Smirnov alex.bluesman.smirnov@gmail.com

arch/arm/mach-mx6/clock.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 8c590b7..8706c32 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -1023,7 +1023,8 @@ static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
__raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
__raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);

•   if (rev >= IMX_CHIP_REVISION_1_1) {
  

•   if ((rev >= IMX_CHIP_REVISION_1_1) &&
  

•       (pllbase == PLL5_VIDEO_BASE_ADDR)) {
          reg = __raw_readl(ANA_MISC2_BASE_ADDR)
                  & ~ANADIG_ANA_MISC2_CONTROL3_MASK;
          reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET;