Fixed VirtARM test and added linux buildroot patches

Author: Alexei Gladkikh

README.md

@@ -20,12 +20,13 @@ import ru.inforion.lab403.kopycat.interfaces.IInteractive
 import ru.inforion.lab403.kopycat.modules.cores.x86Core
 import ru.inforion.lab403.kopycat.serializer.loadValue
 import java.util.logging.Level
+import java.util.logging.Level.*
 
 
 class x86COP(core: x86Core, name: String) : ACOP<x86COP, x86Core>(core, name) {
 
     companion object {
-        val log = logger(Level.INFO)
+        val log = logger(CONFIG)
     }
 
     enum class GateType(val id: Int) {
@@ -117,7 +118,7 @@ class x86COP(core: x86Core, name: String) : ACOP<x86COP, x86Core>(core, name) {
         if (exception is x86HardwareException) {
             error = HardwareError(exception.excCode as ExcCode, exception.errorCode)
             if (exception is x86HardwareException.PageFault) {
-                log.warning { "[${core.pc.hex8}] Page fault for address 0x${exception.address.hex} code=0x${exception.errorCode.hex}" }
+                log.config { "[${core.pc.hex8}] Page fault for address 0x${exception.address.hex} code=0x${exception.errorCode.hex}" }
                 CTRLR.cr2.value(core, exception.address)
             }
             return null
@@ -148,7 +149,7 @@ class x86COP(core: x86Core, name: String) : ACOP<x86COP, x86Core>(core, name) {
         // TODO: Who has higher priority software or hardware interrupt in x86?
         // Currently hardware interrupt has higher priority
             interrupt != null -> {
-                log.config { "Interrupt request: ${interrupt.stringify()}" }
+                log.finest { "Interrupt request: ${interrupt.stringify()}" }
                 interrupt.pending = false
                 interrupt.inService = true
                 interrupt.vector
@@ -185,7 +186,7 @@ class x86COP(core: x86Core, name: String) : ACOP<x86COP, x86Core>(core, name) {
 
         val rpl = cs.cpl(core)
 
-        log.info {
+        log.finest {
             val context = "cpl=$cpl rpl=$rpl ip=${saved_cs.hex}:${saved_ip.hex} sp=${saved_ss.hex}:${saved_sp.hex} flags=${saved_eflags.hex}"
             "--> INT [0x${vector.hex}] IDTR=$idtr hdl=${idtEntry.selector.hex}:${idtEntry.base.hex} $context"
         }

kopycat-modules/cores/x86/src/main/kotlin/ru/inforion/lab403/kopycat/cores/x86/hardware/processors/x86COP.kt

@@ -158,7 +158,7 @@ class IRet(core: x86Core, opcode: ByteArray, prefs: Prefixes):
             else protectedMode()
         }
 
-        log.info {
+        log.finest {
             val prefs = Prefixes(core)
             val ip = x86Register.gpr(prefs.opsize, x86GPR.EIP)
             val sp = x86Register.gpr(prefs.opsize, x86GPR.ESP)

kopycat-modules/cores/x86/src/main/kotlin/ru/inforion/lab403/kopycat/cores/x86/instructions/cpu/branch/IRet.kt

@@ -13,7 +13,7 @@ class Invlpg(core: x86Core, opcode: ByteArray, prefs: Prefixes, vararg operands:
     override val mnem = "invlpg"
     override fun execute() {
         val page = op1.effectiveAddress(core)
-        log.severe { "[${core.pc.hex}] Your TLB cache for 0x${page.hex8} invalidate! Ha-ha-ha..." }
+        log.severe { "[${core.pc.hex}] Your TLB cache for 0x${page.hex8} invalidate!" }
         core.mmu.invalidatePageTranslation(page)
     }
 }

kopycat-modules/cores/x86/src/main/kotlin/ru/inforion/lab403/kopycat/cores/x86/instructions/cpu/control/Invlpg.kt

@@ -10,6 +10,7 @@ class Hlt(core: x86Core, opcode: ByteArray, prefs: Prefixes):
     override val mnem = "hlt"
 
     override fun execute() {
+        // log.config { "Processor halt -> wait for interrupt" }
         core.cpu.halted = true
     }
 }

kopycat-modules/cores/x86/src/main/kotlin/ru/inforion/lab403/kopycat/cores/x86/instructions/cpu/system/Hlt.kt

@@ -327,7 +327,7 @@ abstract class x86Register(
         object cr2 : CTRLR(eCTRLR.CR2.id)
         object cr3 : CTRLR(eCTRLR.CR3.id) {
             override fun value(core: x86Core, data: Long) {
-                log.severe { "[${core.pc.hex}] CR3 register changed to ${data.hex} -> paging cache invalidated!" }
+                log.fine { "[${core.pc.hex}] CR3 register changed to ${data.hex} -> paging cache invalidated!" }
                 core.cpu.cregs.writeIntern(reg, data)
                 core.mmu.invalidatePagingCache()
             }

kopycat-modules/cores/x86/src/main/kotlin/ru/inforion/lab403/kopycat/cores/x86/operands/x86Register.kt

@@ -17,7 +17,6 @@ import java.util.logging.Level.FINE
 import java.util.logging.Level.FINER
 
 @Suppress("MemberVisibilityCanBePrivate", "PropertyName")
-
 class PIT(parent: Module, name: String) : Module(parent, name) {
     companion object {
         val log = logger(FINE)
@@ -239,7 +238,7 @@ class PIT(parent: Module, name: String) : Module(parent, name) {
                             if (it.COUNT == 0) {
                                 ports.irq.request(it.id)
                                 it.COUNT = it.LATCHED
-                                log.fine { "%s counter reached latched value at %,d ns".format(name, core.clock.time(Time.ns)) }
+                                log.finest { "%s counter reached latched value at %,d ns".format(name, core.clock.time(Time.ns)) }
                             }
                         }
                 else -> TODO("Timer mode not implemented yet or not supported ${PITMODECTL.CTR_MODE}")