High level design plans

Performance

• C generation almost acceptable (faster vtable init left)
• Python is slow. pypy plus static typing annotations, or reimplement parts in rust?
• Develop DML code generator practices for avoiding huge banks
• Dynamic register_view
• Hands-on help for SSM and PSG infra

Coroutines

• hooks/channels

Conditional imports

• may come with a larger loosening of order dependency rules for early evaluated expressions, i.e., early cross-obj param refs are ok if param dependency graph doesn't have cycles

Dynamic objects

Two options: A. Truly dynamic objects, e.g. instantiation-time config of array sizes B. Optionally hidden elements, e.g. disabled registers

• dynamic ports are problematic, port arrays can't be port objects