Remove 32-bit x86 architecture support

As already announced in issue #296, we are removing 32-bit x86 support,
which was not being validated anyway.

Signed-off-by: Pablo de Lara <[email protected]>

Author: pablodelara

Makefile.am

@@ -26,19 +26,13 @@ perf_tests_extra=
 examples=
 other_tests=
 other_tests_x86_64=
-other_tests_x86_32=
-other_tests_aarch64=
 other_tests_ppc64le=
 other_tests_riscv64=
 lsrc_x86_64=
-lsrc_x86_32=
 lsrc_aarch64=
 lsrc_ppc64le=
 lsrc_riscv64=
 lsrc_base_aliases=
-lsrc32=
-unit_tests32=
-perf_tests32=
 progs=
 
 # Include units
@@ -67,12 +61,6 @@ libisal_la_SOURCES += ${lsrc_x86_64}
 other_tests += ${other_tests_x86_64}
 endif
 
-if CPU_X86_32
-ARCH=-Dx86_32
-libisal_la_SOURCES += ${lsrc_x86_32}
-other_tests += ${other_tests_x86_32}
-endif
-
 if CPU_AARCH64
 ARCH=-Daarch64
 libisal_la_SOURCES += ${lsrc_aarch64}

Release_notes.txt

@@ -9,10 +9,6 @@ RELEASE NOTE CONTENTS
 1. KNOWN ISSUES
 ----------------
 
-* 32-bit lib is not supported in Windows.
-
-* 32-bit lib is not validated.
-
 2. FIXED ISSUES
 ---------------
 v2.31.1
@@ -143,6 +139,7 @@ v2.32
 
 * General:
   - Minimum NASM version required for x86 architecture is 2.14.01 now.
+  - 32-bit x86 support has been removed.
 
 * RISCV support.
   - Initial riscv64 support with runtime and build-time CPU feature detection.

configure.ac

@@ -26,15 +26,13 @@ CPU=""
 AS_CASE([$host_cpu],
   [x86_64], [CPU="x86_64"],
   [amd64], [CPU="x86_64"],
-  [i?86], [CPU="x86_32"],
   [aarch64], [CPU="aarch64"],
   [arm64], [CPU="aarch64"],
   [powerpc64le], [CPU="ppc64le"],
   [ppc64le], [CPU="ppc64le"],
   [riscv64], [CPU="riscv64"],
 )
 AM_CONDITIONAL([CPU_X86_64], [test "$CPU" = "x86_64"])
-AM_CONDITIONAL([CPU_X86_32], [test "$CPU" = "x86_32"])
 AM_CONDITIONAL([CPU_AARCH64], [test "$CPU" = "aarch64"])
 AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
 AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
@@ -57,11 +55,6 @@ case "${CPU}" in
 		is_x86=yes
 		;;
 
-	x86_32)
-
-		is_x86=yes
-		;;
-
 	riscv64)
 
 		AC_MSG_CHECKING([checking RVV support])

crc/Makefile.am

@@ -34,7 +34,6 @@ lsrc  += \
 	crc/crc64_base.c
 
 lsrc_base_aliases += crc/crc_base_aliases.c
-lsrc_x86_32       += crc/crc_base_aliases.c
 lsrc_ppc64le      += crc/crc_base_aliases.c
 lsrc_riscv64      += crc/crc_base_aliases.c
 

erasure_code/Makefile.am

@@ -113,35 +113,6 @@ lsrc_x86_64  += \
 		erasure_code/gf_5vect_mad_avx512_gfni.asm \
 		erasure_code/gf_6vect_mad_avx512_gfni.asm
 
-lsrc_x86_32  += \
-		erasure_code/ec_highlevel_func.c \
-		erasure_code/ec_multibinary.asm \
-		erasure_code/gf_vect_dot_prod_avx.asm \
-		erasure_code/gf_2vect_dot_prod_avx.asm \
-		erasure_code/gf_3vect_dot_prod_avx.asm \
-		erasure_code/gf_4vect_dot_prod_avx.asm \
-		erasure_code/gf_vect_dot_prod_sse.asm \
-		erasure_code/gf_2vect_dot_prod_sse.asm \
-		erasure_code/gf_3vect_dot_prod_sse.asm \
-		erasure_code/gf_4vect_dot_prod_sse.asm \
-		erasure_code/gf_vect_dot_prod_avx2.asm \
-		erasure_code/gf_2vect_dot_prod_avx2.asm \
-		erasure_code/gf_3vect_dot_prod_avx2.asm \
-		erasure_code/gf_4vect_dot_prod_avx2.asm
-
-unit_tests32 += erasure_code/erasure_code_base_test \
-		erasure_code/erasure_code_test \
-		erasure_code/gf_vect_mul_test \
-		erasure_code/gf_vect_mul_base_test \
-		erasure_code/gf_vect_dot_prod_base_test \
-		erasure_code/gf_vect_dot_prod_test
-
-perf_tests32 += erasure_code/gf_vect_mul_perf \
-		erasure_code/gf_vect_dot_prod_perf \
-		erasure_code/erasure_code_perf \
-		erasure_code/erasure_code_base_perf \
-		erasure_code/gf_vect_dot_prod_1tbl
-
 src_include += -I $(srcdir)/erasure_code
 extern_hdrs  += include/erasure_code.h \
 		include/gf_vect_mul.h

erasure_code/ec_multibinary.asm

@@ -30,26 +30,22 @@
 %include "reg_sizes.asm"
 %include "multibinary.asm"
 
-%ifidn __OUTPUT_FORMAT__, elf32
- [bits 32]
-%else
- default rel
- [bits 64]
+default rel
+[bits 64]
 
- extern ec_encode_data_update_sse
- extern ec_encode_data_update_avx
- extern ec_encode_data_update_avx2
- extern ec_encode_data_avx512
- extern gf_vect_dot_prod_avx512
- extern ec_encode_data_update_avx512
- extern gf_vect_mad_avx512
- extern gf_vect_mul_sse
- extern gf_vect_mul_avx
+extern ec_encode_data_update_sse
+extern ec_encode_data_update_avx
+extern ec_encode_data_update_avx2
+extern ec_encode_data_avx512
+extern gf_vect_dot_prod_avx512
+extern ec_encode_data_update_avx512
+extern gf_vect_mad_avx512
+extern gf_vect_mul_sse
+extern gf_vect_mul_avx
 
- extern gf_vect_mad_sse
- extern gf_vect_mad_avx
- extern gf_vect_mad_avx2
-%endif
+extern gf_vect_mad_sse
+extern gf_vect_mad_avx
+extern gf_vect_mad_avx2
 
 extern ec_init_tables_gfni
 extern ec_encode_data_avx512_gfni
@@ -79,19 +75,9 @@ mbin_interface ec_encode_data_update
 mbin_interface gf_vect_mad
 mbin_interface ec_init_tables
 
-%ifidn __OUTPUT_FORMAT__, elf32
- mbin_dispatch_init5 ec_encode_data, ec_encode_data_base, ec_encode_data_sse, ec_encode_data_avx, ec_encode_data_avx2
- mbin_dispatch_init5 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2
- mbin_dispatch_init2 gf_vect_mul, gf_vect_mul_base
- mbin_dispatch_init2 ec_encode_data_update, ec_encode_data_update_base
- mbin_dispatch_init2 gf_vect_mad, gf_vect_mad_base
- mbin_dispatch_init2 ec_init_tables, ec_init_tables_base
-%else
-
- mbin_dispatch_init5 gf_vect_mul, gf_vect_mul_base, gf_vect_mul_sse, gf_vect_mul_avx, gf_vect_mul_avx
- mbin_dispatch_init8 ec_encode_data, ec_encode_data_base, ec_encode_data_sse, ec_encode_data_avx, ec_encode_data_avx2, ec_encode_data_avx512, ec_encode_data_avx2_gfni, ec_encode_data_avx512_gfni
- mbin_dispatch_init8 ec_encode_data_update, ec_encode_data_update_base, ec_encode_data_update_sse, ec_encode_data_update_avx, ec_encode_data_update_avx2, ec_encode_data_update_avx512, ec_encode_data_update_avx2_gfni, ec_encode_data_update_avx512_gfni
- mbin_dispatch_init6 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2, gf_vect_mad_avx512
- mbin_dispatch_init6 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2, gf_vect_dot_prod_avx512
- mbin_dispatch_init8 ec_init_tables, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_gfni, ec_init_tables_gfni
-%endif
+mbin_dispatch_init5 gf_vect_mul, gf_vect_mul_base, gf_vect_mul_sse, gf_vect_mul_avx, gf_vect_mul_avx
+mbin_dispatch_init8 ec_encode_data, ec_encode_data_base, ec_encode_data_sse, ec_encode_data_avx, ec_encode_data_avx2, ec_encode_data_avx512, ec_encode_data_avx2_gfni, ec_encode_data_avx512_gfni
+mbin_dispatch_init8 ec_encode_data_update, ec_encode_data_update_base, ec_encode_data_update_sse, ec_encode_data_update_avx, ec_encode_data_update_avx2, ec_encode_data_update_avx512, ec_encode_data_update_avx2_gfni, ec_encode_data_update_avx512_gfni
+mbin_dispatch_init6 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2, gf_vect_mad_avx512
+mbin_dispatch_init6 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2, gf_vect_dot_prod_avx512
+mbin_dispatch_init8 ec_init_tables, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_base, ec_init_tables_gfni, ec_init_tables_gfni

erasure_code/gf_2vect_dot_prod_avx.asm

@@ -105,74 +105,6 @@
  %endmacro
 %endif
 
-%ifidn __OUTPUT_FORMAT__, elf32
-
-;;;================== High Address;
-;;;	arg4
-;;;	arg3
-;;;	arg2
-;;;	arg1
-;;;	arg0
-;;;	return
-;;;<================= esp of caller
-;;;	ebp
-;;;<================= ebp = esp
-;;;	var0
-;;;	esi
-;;;	edi
-;;;	ebx
-;;;<================= esp of callee
-;;;
-;;;================== Low Address;
-
- %define PS 4
- %define LOG_PS 2
- %define func(x) x: endbranch
- %define arg(x) [ebp + PS*2 + PS*x]
- %define var(x) [ebp - PS - PS*x]
-
- %define trans   ecx
- %define trans2  esi
- %define arg0    trans		;trans and trans2 are for the variables in stack
- %define arg0_m  arg(0)
- %define arg1    ebx
- %define arg2    arg2_m
- %define arg2_m  arg(2)
- %define arg3    trans
- %define arg3_m  arg(3)
- %define arg4    trans
- %define arg4_m  arg(4)
- %define tmp	 edx
- %define tmp2    edi
- %define tmp3    trans2
- %define tmp4    trans2
- %define tmp4_m  var(0)
- %define return  eax
- %macro SLDR 2	;; stack load/restore
-	mov %1, %2
- %endmacro
- %define SSTR SLDR
-
- %macro FUNC_SAVE 0
-	push	ebp
-	mov	ebp, esp
-	sub	esp, PS*1	;1 local variable
-	push	esi
-	push	edi
-	push	ebx
-	mov	arg1, arg(1)
- %endmacro
-
- %macro FUNC_RESTORE 0
-	pop	ebx
-	pop	edi
-	pop	esi
-	add	esp, PS*1	;1 local variable
-	pop	ebp
- %endmacro
-
-%endif	; output formats
-
 %define len   arg0
 %define vec   arg1
 %define mul_array arg2
@@ -184,13 +116,6 @@
 %define dest2 tmp4
 %define pos   return
 
- %ifidn PS,4				;32-bit code
-	%define  len_m 	arg0_m
-	%define  src_m 	arg3_m
-	%define  dest1_m arg4_m
-	%define  dest2_m tmp4_m
- %endif
-
 %ifndef EC_ALIGNED_ADDR
 ;;; Use Un-aligned load/store
  %define XLDR vmovdqu
@@ -206,36 +131,21 @@
  %endif
 %endif
 
-%ifidn PS,8			; 64-bit code
- default rel
-  [bits 64]
-%endif
+default rel
+[bits 64]
 
 section .text
 
-%ifidn PS,8			;64-bit code
- %define xmask0f   xmm8
- %define xgft1_lo  xmm7
- %define xgft1_hi  xmm6
- %define xgft2_lo  xmm5
- %define xgft2_hi  xmm4
-
- %define x0     xmm0
- %define xtmpa  xmm1
- %define xp1    xmm2
- %define xp2    xmm3
-%else				;32-bit code
- %define xmask0f   xmm4
- %define xgft1_lo  xmm7
- %define xgft1_hi  xmm6
- %define xgft2_lo  xgft1_lo
- %define xgft2_hi  xgft1_hi
-
- %define x0     xmm0
- %define xtmpa  xmm1
- %define xp1    xmm2
- %define xp2    xmm3
-%endif
+%define xmask0f   xmm8
+%define xgft1_lo  xmm7
+%define xgft1_hi  xmm6
+%define xgft2_lo  xmm5
+%define xgft2_hi  xmm4
+
+%define x0     xmm0
+%define xtmpa  xmm1
+%define xp1    xmm2
+%define xp2    xmm3
 
 align 16
 mk_global gf_2vect_dot_prod_avx, function
@@ -267,12 +177,10 @@ func(gf_2vect_dot_prod_avx)
 
 	vmovdqu	xgft1_lo, [tmp]		;Load array Ax{00}, Ax{01}, ..., Ax{0f}
 	vmovdqu	xgft1_hi, [tmp+16]	;     "     Ax{00}, Ax{10}, ..., Ax{f0}
- %ifidn PS,8				; 64-bit code
 	vmovdqu	xgft2_lo, [tmp+vec*(32/PS)]	;Load array Bx{00}, Bx{01}, ..., Bx{0f}
 	vmovdqu	xgft2_hi, [tmp+vec*(32/PS)+16]	;     "     Bx{00}, Bx{10}, ..., Bx{f0}
 	add	tmp, 32
 	add	vec_i, PS
- %endif
 	XLDR	x0, [ptr+pos]		;Get next source vector
 
 	vpand	xtmpa, x0, xmask0f	;Mask low src nibble in bits 4-0
@@ -284,12 +192,6 @@ func(gf_2vect_dot_prod_avx)
 	vpxor	xgft1_hi, xgft1_lo	;GF add high and low partials
 	vpxor	xp1, xgft1_hi		;xp1 += partial
 
- %ifidn PS,4				; 32-bit code
-	vmovdqu	xgft2_lo, [tmp+vec*(32/PS)]	;Load array Bx{00}, Bx{01}, ..., Bx{0f}
-	vmovdqu	xgft2_hi, [tmp+vec*(32/PS)+16]	;     "     Bx{00}, Bx{10}, ..., Bx{f0}
-	add	tmp, 32
-	add	vec_i, PS
- %endif
 	vpshufb	xgft2_hi, x0		;Lookup mul table of high nibble
 	vpshufb	xgft2_lo, xtmpa		;Lookup mul table of low nibble
 	vpxor	xgft2_hi, xgft2_lo	;GF add high and low partials