Skip to content

[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE #29772

[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE

[SYCL] PR 6 - Remove FPGA Attributes from SYCL FE #29772

Annotations

1 warning

run_prebuilt_e2e_tests (Intel GEN12 Graphics with Level Zero, ["Windows","gen12"])  /  Intel GEN12 Graphics with Level Zero

succeeded Apr 15, 2026 in 5m 44s