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LhGuintel-mediadev
LhGu
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intel-mediadev
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[Media Common] NVL-S Linux DDI Layer Upstreaming
NVL-S Linux DDI Layer Upstreaming, This patch is just part of NVLS code, it does not officially enable NVLS support. More patches will follow. The availability of NVLS will be announced in the readme.
1 parent 4eaa389 commit 3202761

36 files changed

+3257
-0
lines changed

‎media_softlet/linux/media_srcs.cmake‎

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@@ -41,4 +41,9 @@ endif()
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if(XE3_LPM_SUPPORT)
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media_include_subdirectory(xe3_lpm)
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media_include_subdirectory(xe3_lpm_r0)
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endif()
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if(XE3P_LPM_SUPPORT)
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media_include_subdirectory(xe3p_lpm)
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media_include_subdirectory(xe3p_lpm_r0)
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endif()

‎media_softlet/linux/xe3p_lpm/ddi/caps_register_specific_xe3p_lpm.cpp‎

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/*
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* Copyright (c) 2025, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
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* The above copyright notice and this permission notice shall be included
12+
* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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//!
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//! \file caps_register_specific_xe3p_lpm.cpp
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//! \brief This file register all caps data for xe3p_lpm
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//!
26+
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// Only for new platforms init, should be removed once new platform caps init done
28+
#include "capstable_data_xe3p_lpm_r0_specific.h"
29+
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// Static initialization to register capabilities table for xe3p_lpm_r0 platform
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// The return value is intentionally unused - only the registration side effect matters
32+
static bool capsTableXe3p_Lpm_r0Registered = MediaCapsTable<CapsData>::RegisterCaps(plt_Xe3p_Lpm_r0, capsData_Xe3p_Lpm_r0);

‎media_softlet/linux/xe3p_lpm/ddi/media_sku_wa_nvls.cpp‎

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/*
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* Copyright (c) 2025, Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
6+
* to deal in the Software without restriction, including without limitation
7+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
11+
* The above copyright notice and this permission notice shall be included
12+
* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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//!
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//! \file media_sku_wa_nvls.cpp
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//!
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#include "igfxfmid.h"
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#include "linux_system_info.h"
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#include "skuwa_factory.h"
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#include "linux_skuwa_debug.h"
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#include "linux_media_skuwa.h"
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#include "media_user_setting_specific.h"
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static constexpr uint32_t singleVeboxSubSliceNumMax = 24;
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//extern template class DeviceInfoFactory<GfxDeviceInfo>;
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typedef DeviceInfoFactory<LinuxDeviceInit> DeviceInit;
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static struct LinuxCodecInfo nvlCodecInfo =
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{
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.avcDecoding = 1,
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.mpeg2Decoding = 1,
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.vp8Decoding = 1,
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.vc1Decoding = 0,
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.jpegDecoding = 1,
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.avcEncoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
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.mpeg2Encoding = 0,
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.hevcDecoding = 1,
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.hevcEncoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
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.jpegEncoding = 1,
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.avcVdenc = 1,
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.vp9Decoding = 1,
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.hevc10Decoding = 1,
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.vp9b10Decoding = 1,
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.hevc10Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
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.hevc12Encoding = 0,
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.vp8Encoding = 0,
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.hevcVdenc = 1,
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.vp9Vdenc = 1,
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.adv0Decoding = 1,
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.adv1Decoding = 1,
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};
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static bool InitNvlMediaSkuExt(struct GfxDeviceInfo *devInfo,
65+
MediaFeatureTable *skuTable,
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struct LinuxDriverInfo *drvInfo,
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MediaUserSettingSharedPtr userSettingPtr)
68+
{
69+
if ((devInfo == nullptr) || (skuTable == nullptr) || (drvInfo == nullptr))
70+
{
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DEVINFO_ERROR("null ptr is passed\n");
72+
return false;
73+
}
74+
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if (drvInfo->hasBsd)
76+
{
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LinuxCodecInfo *codecInfo = &nvlCodecInfo;
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MEDIA_WR_SKU(skuTable, FtrAVCVLDLongDecoding, codecInfo->avcDecoding);
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MEDIA_WR_SKU(skuTable, FtrIntelAVCVLDHigh422Decoding, codecInfo->avcDecoding);
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MEDIA_WR_SKU(skuTable, FtrMPEG2VLDDecoding, codecInfo->mpeg2Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelVP8VLDDecoding, codecInfo->vp8Decoding);
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MEDIA_WR_SKU(skuTable, FtrVC1VLDDecoding, codecInfo->vc1Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelJPEGDecoding, codecInfo->jpegDecoding);
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MEDIA_WR_SKU(skuTable, FtrEncodeAVC, codecInfo->avcEncoding);
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MEDIA_WR_SKU(skuTable, FtrEncodeMPEG2, codecInfo->mpeg2Encoding);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMainDecoding, codecInfo->hevcDecoding);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10Decoding, codecInfo->hevc10Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelVVCVLDDecodingMain10, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelVVCVLDDecodingMultilayerMain10, 0);
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVC, codecInfo->hevcEncoding);
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVC10bit, codecInfo->hevc10Encoding);
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MEDIA_WR_SKU(skuTable, FtrEncodeJPEG, codecInfo->jpegEncoding);
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MEDIA_WR_SKU(skuTable, FtrEncodeAVCVdenc, codecInfo->avcVdenc);
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MEDIA_WR_SKU(skuTable, FtrVP9VLDDecoding, codecInfo->vp9Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile0Decoding8bit420, codecInfo->vp9Decoding);
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MEDIA_WR_SKU(skuTable, FtrVP9VLD10bProfile2Decoding, codecInfo->vp9b10Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile2Decoding, codecInfo->vp9b10Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelAV1VLDDecoding8bit420, codecInfo->adv0Decoding);
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MEDIA_WR_SKU(skuTable, FtrAV1VLDProfile1Decoding8bit444, codecInfo->adv0Decoding);
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MEDIA_WR_SKU(skuTable, FtrIntelAV1VLDDecoding10bit420, codecInfo->adv1Decoding);
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MEDIA_WR_SKU(skuTable, FtrAV1VLDProfile1Decoding10bit444, codecInfo->adv1Decoding);
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/* HEVC VDENC */
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain, codecInfo->hevcVdenc);
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10, codecInfo->hevcVdenc);
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/* Vp9 VDENC */
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MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc, codecInfo->vp9Vdenc);
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/* HEVC Main8/10bit-422/444 Decoding. Currently it is enabled. */
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD42210bitDecoding, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD4448bitDecoding, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD44410bitDecoding, 1);
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/* SFC Histogram Streamout. */
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MEDIA_WR_SKU(skuTable, FtrSFCHistogramStreamOut, 1);
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/* Subset buffer for realtile decoding. */
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDDecodingSubsetBuffer, 1);
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/* HEVC Main8/10bit-420/422/444 Scc Decoding. Currently it is enabled. */
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain8bit420SCC, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10bit420SCC, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain8bit444SCC, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10bit444SCC, 1);
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/* HEVC VDENC Main8/10 422/444 Encoding. */
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain444, codecInfo->hevcVdenc);
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain422, codecInfo->hevcVdenc);
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit422, codecInfo->hevcVdenc);
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MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit444, codecInfo->hevcVdenc);
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/* HEVC 12bit Decoding. Currently it is enabled */
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit420Decoding, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit422Decoding, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit444Decoding, 1);
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/* VP9 8 bit 444 */
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MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile1Decoding8bit444, 1);
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/* VP9 10 Bit 444*/
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MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile3Decoding10bit444, 1);
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/* VP9 12 bit 420/444 */
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MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile2Decoding12bit420, 1);
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MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile3Decoding12bit444, 1);
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/* VP9 VDENC 8Bit 444 */
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MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc8bit444, codecInfo->vp9Vdenc);
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/* VP9 VDENC 10Bit 420/444 */
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MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc10bit420, codecInfo->vp9Vdenc);
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MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc10bit444, codecInfo->vp9Vdenc);
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/* AV1 VDENC 8/10Bit 420 */
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MEDIA_WR_SKU(skuTable, FtrEncodeAV1Vdenc, 1);
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MEDIA_WR_SKU(skuTable, FtrEncodeAV1Vdenc10bit420, 1);
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}
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159+
MEDIA_WR_SKU(skuTable, FtrEnableProtectedHuc, drvInfo->hasProtectedHuc);
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MEDIA_WR_SKU(skuTable, FtrEnableMediaKernels, drvInfo->hasHuc);
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MEDIA_WR_SKU(skuTable, FtrVERing, drvInfo->hasVebox);
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MEDIA_WR_SKU(skuTable, FtrPPGTT, drvInfo->hasPpgtt);
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MEDIA_WR_SKU(skuTable, FtrEDram, devInfo->hasERAM);
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MEDIA_WR_SKU(skuTable, FtrPPGTTBasedHuCLoad, 1);
165+
166+
MEDIA_WR_SKU(skuTable, FtrSingleVeboxSlice, 1);
167+
if (devInfo->SubSliceCount >= singleVeboxSubSliceNumMax)
168+
{
169+
MEDIA_WR_SKU(skuTable, FtrSingleVeboxSlice, 0);
170+
}
171+
172+
MEDIA_WR_SKU(skuTable, FtrSFCPipe, 1);
173+
MEDIA_WR_SKU(skuTable, FtrHCP2SFCPipe, 1);
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MEDIA_WR_SKU(skuTable, FtrSSEUPowerGating, 1);
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MEDIA_WR_SKU(skuTable, FtrSSEUPowerGatingControlByUMD, 1);
176+
177+
MEDIA_WR_SKU(skuTable, FtrPerCtxtPreemptionGranularityControl, 1);
178+
179+
/* It is disabled by default. It can be enabled based on HW */
180+
MEDIA_WR_SKU(skuTable, FtrMemoryCompression, 0);
181+
MEDIA_WR_SKU(skuTable, FtrHcpDecMemoryCompression, 0);
182+
MEDIA_WR_SKU(skuTable, Ftr10bitDecMemoryCompression, 0);
183+
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MEDIA_WR_SKU(skuTable, FtrCCSNode, 1);
185+
186+
MEDIA_WR_SKU(skuTable, FtrVpP010Output, 1);
187+
MEDIA_WR_SKU(skuTable, FtrVp10BitSupport, 1);
188+
MEDIA_WR_SKU(skuTable, FtrVp16BitSupport, 1);
189+
190+
MEDIA_WR_SKU(skuTable, FtrContextBasedScheduling, 1);
191+
MEDIA_WR_SKU(skuTable, FtrSfcScalability, 1);
192+
193+
MEDIA_WR_SKU(skuTable, FtrSWMediaReset, 1);
194+
MEDIA_WR_SKU(skuTable, FtrGucSubmission, 1);
195+
196+
MEDIA_WR_SKU(skuTable, FtrTileY, 0);
197+
MEDIA_WR_SKU(skuTable, FtrLinearCCS, 1);
198+
MEDIA_WR_SKU(skuTable, FtrFlatPhysCCS, 1);
199+
200+
MEDIA_WR_SKU(skuTable, FtrWithSlimVdbox, 0);
201+
202+
MEDIA_WR_SKU(skuTable, FtrE2ECompression, 1);
203+
MEDIA_WR_SKU(skuTable, FtrXe2Compression , 1);
204+
MEDIA_WR_SKU(skuTable, FtrHDR, 1);
205+
MEDIA_WR_SKU(skuTable, FtrDisableRenderTargetWidthAdjust, 1);
206+
207+
MOS_USER_FEATURE_VALUE_DATA userFeatureData;
208+
// Disable MMC for all components if set reg key
209+
MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
210+
MOS_UserFeature_ReadValue_ID(
211+
nullptr,
212+
__MEDIA_USER_FEATURE_VALUE_DISABLE_MMC_ID,
213+
&userFeatureData,
214+
(MOS_CONTEXT_HANDLE)nullptr);
215+
if (userFeatureData.bData)
216+
{
217+
MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
218+
MEDIA_WR_SKU(skuTable, FtrXe2Compression , 0);
219+
}
220+
221+
// Create uncompressible surface by default
222+
MEDIA_WR_SKU(skuTable, FtrCompressibleSurfaceDefault, 0);
223+
224+
bool compressibleSurfaceEnable = false;
225+
226+
ReadUserSetting(userSettingPtr,
227+
compressibleSurfaceEnable,
228+
"Enable Compressible Surface Creation",
229+
MediaUserSetting::Group::Device);
230+
231+
if (compressibleSurfaceEnable)
232+
{
233+
MEDIA_WR_SKU(skuTable, FtrCompressibleSurfaceDefault, 1);
234+
}
235+
236+
//Disable LocalMemory for all iGraphics
237+
MEDIA_WR_SKU(skuTable, FtrLocalMemory, 0);
238+
239+
MEDIA_WR_SKU(skuTable, FtrConditionalBatchBuffEnd, 1);
240+
MEDIA_WR_SKU(skuTable, FtrUseSwSwizzling, 0);
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MEDIA_WR_SKU(skuTable, FtrMemoryRemapSupport, 1);
242+
243+
MEDIA_WR_SKU(skuTable, FtrAV1VLDLSTDecoding, 1);
244+
MEDIA_WR_SKU(skuTable, FtrMediaIPSeparation , 1);
245+
246+
return true;
247+
}
248+
249+
static bool InitNvlMediaWaExt(struct GfxDeviceInfo *devInfo,
250+
MediaWaTable *waTable,
251+
struct LinuxDriverInfo *drvInfo)
252+
{
253+
if ((devInfo == nullptr) || (waTable == nullptr) || (drvInfo == nullptr))
254+
{
255+
DEVINFO_ERROR("null ptr is passed\n");
256+
return false;
257+
}
258+
259+
MEDIA_WR_WA(waTable, WaForceGlobalGTT, !drvInfo->hasPpgtt);
260+
MEDIA_WR_WA(waTable, WaMidBatchPreemption, 0);
261+
MEDIA_WR_WA(waTable, WaArbitraryNumMbsInSlice, 1);
262+
263+
MEDIA_WR_WA(waTable, WaSFC270DegreeRotation, 0);
264+
265+
MEDIA_WR_WA(waTable, WaEnableYV12BugFixInHalfSliceChicken7, 1);
266+
267+
/*software wa to disable calculate the UV offset by gmmlib
268+
CPU blt call will add/remove padding on the platform*/
269+
MEDIA_WR_WA(waTable, WaDisableGmmLibOffsetInDeriveImage, 0);
270+
271+
/* Turn off MMC for codec, need to remove once turn it on */
272+
MEDIA_WR_WA(waTable, WaDisableCodecMmc, 0);
273+
274+
/* Turn off MMC for VPP, need to remove once turn it on */
275+
MEDIA_WR_WA(waTable, WaDisableVPMmc, 0);
276+
277+
MEDIA_WR_WA(waTable, WaDisableSetObjectCapture, 1);
278+
279+
MEDIA_WR_WA(waTable, Wa_Vp9UnalignedHeight, 0);
280+
281+
MEDIA_WR_WA(waTable, Wa_22018691483, 1);
282+
MEDIA_WR_WA(waTable, Wa_15017419530, 1);
283+
MEDIA_WR_WA(waTable, Wa_15017726119, 1);
284+
MEDIA_WR_WA(waTable, Wa_16027316307, 1);
285+
MEDIA_WR_WA(waTable, Wa_16025947269, 1);
286+
287+
return true;
288+
}
289+
290+
static struct LinuxDeviceInit nvlXe3GDeviceInit =
291+
{
292+
.productFamily = IGFX_NVL_XE3G,
293+
.InitMediaFeature = InitNvlMediaSkuExt,
294+
.InitMediaWa = InitNvlMediaWaExt,
295+
};
296+
297+
static bool nvlXe3GDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
298+
RegisterDevice(IGFX_NVL_XE3G, &nvlXe3GDeviceInit);

‎media_softlet/linux/xe3p_lpm/ddi/media_srcs.cmake‎

Lines changed: 35 additions & 0 deletions
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1+
# Copyright (c) 2025, Intel Corporation
2+
#
3+
# Permission is hereby granted, free of charge, to any person obtaining a
4+
# copy of this software and associated documentation files (the "Software"),
5+
# to deal in the Software without restriction, including without limitation
6+
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
7+
# and/or sell copies of the Software, and to permit persons to whom the
8+
# Software is furnished to do so, subject to the following conditions:
9+
#
10+
# The above copyright notice and this permission notice shall be included
11+
# in all copies or substantial portions of the Software.
12+
#
13+
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
14+
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15+
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16+
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
17+
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18+
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19+
# OTHER DEALINGS IN THE SOFTWARE.
20+
21+
set(TMP_SOURCES_
22+
${CMAKE_CURRENT_LIST_DIR}/caps_register_specific_xe3p_lpm.cpp
23+
${CMAKE_CURRENT_LIST_DIR}/media_sysinfo_nvls.cpp
24+
${CMAKE_CURRENT_LIST_DIR}/media_sku_wa_nvls.cpp
25+
)
26+
27+
set(SOFTLET_DDI_SOURCES_
28+
${SOFTLET_DDI_SOURCES_}
29+
${TMP_SOURCES_}
30+
)
31+
32+
set(SOFTLET_DDI_PUBLIC_INCLUDE_DIRS_
33+
${SOFTLET_DDI_PUBLIC_INCLUDE_DIRS_}
34+
${CMAKE_CURRENT_LIST_DIR}
35+
)

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