Motivation

Currently, Cosim is defined as mixin Cosim on ExternalSystemVerilogModule. It should be posisble to add a Cosim mixin on any Module, rather than just ExternalSystemVerilogModule. This opens the door to inheriting from Module (or some other base class that extends Module) and still use the Cosim mixin. For example, if there's a ROHD version and a SystemVerilog version of the same design, it would make sense to have a base-class with port definitions, etc. and reuse it for both the ROHD and Cosim versions.

Desired solution

Make Cosim on Module, and whatever other changes are needed to support it.

Alternatives considered

No response

Additional details

No response