From 55b09045fae8b3a49dc6312e20f979780ae636c9 Mon Sep 17 00:00:00 2001 From: Max Korbel Date: Fri, 25 Apr 2025 12:22:18 -0700 Subject: [PATCH 1/3] Initial infra for conditional cosimulation --- lib/src/cosim.dart | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/lib/src/cosim.dart b/lib/src/cosim.dart index 069b7b8..ba13b0a 100644 --- a/lib/src/cosim.dart +++ b/lib/src/cosim.dart @@ -72,7 +72,7 @@ class _CosimMessage { /// When applied to a [ExternalSystemVerilogModule], will configure it so that /// it can be cosimulated in a SystemVerilog simulator along with the ROHD /// simulator. -mixin Cosim on ExternalSystemVerilogModule { +mixin Cosim on SystemVerilog { /// A list of verilog source files to include in the build. /// /// The contents are put in a Makefile, so environment variables should use @@ -108,6 +108,13 @@ mixin Cosim on ExternalSystemVerilogModule { /// module to something else. String get cosimHierarchy => registreeName; + /// If set, then this [Module] will be registered for cosimulation. + /// + /// This flag can be used to determine whether additional modelling logic or + /// design should be generated within the module or if it should be left to + /// cosimulation to handle behavior. + bool get cosimEnabled => true; + /// Resets all context for cosimulation. /// /// Note that any [Cosim]s already built will need to be reregistered via @@ -163,7 +170,9 @@ mixin Cosim on ExternalSystemVerilogModule { @override Future build() async { - cosimRegister(); + if (cosimEnabled) { + cosimRegister(); + } await super.build(); } From 9e1e51e3796659bb7d86dbe93fc487ac670d7ff9 Mon Sep 17 00:00:00 2001 From: Max Korbel Date: Fri, 25 Apr 2025 15:47:49 -0700 Subject: [PATCH 2/3] adjustment for non-external --- lib/src/configs/cosim_wrap_config.dart | 34 ++++++++++++++++++-------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/lib/src/configs/cosim_wrap_config.dart b/lib/src/configs/cosim_wrap_config.dart index 4b3e435..51c80a1 100644 --- a/lib/src/configs/cosim_wrap_config.dart +++ b/lib/src/configs/cosim_wrap_config.dart @@ -9,6 +9,7 @@ import 'dart:io'; +import 'package:rohd/rohd.dart'; import 'package:rohd_cosim/rohd_cosim.dart'; /// A selection of a type of SystemVerilog Simulator. @@ -139,16 +140,29 @@ class CosimWrapConfig extends CosimProcessConfig { {String? dumpWavesString}) { final wrapperVerilog = [ 'module $_wrapperName();', - ...registrees.entries - .map((registreeEntry) => registreeEntry.value.instantiationVerilog( - 'dont_care', - registreeEntry.key, - { - ...registreeEntry.value.inputs, - ...registreeEntry.value.outputs, - ...registreeEntry.value.inOuts, - }.map((key, value) => MapEntry(key, '')), - )), + ...registrees.entries.map((registreeEntry) { + const instanceType = 'dont_care'; + final instanceName = registreeEntry.key; + final module = registreeEntry.value; + final ports = { + ...registreeEntry.value.inputs, + ...registreeEntry.value.outputs, + ...registreeEntry.value.inOuts, + }.map((key, value) => MapEntry(key, '')); + + return module.instantiationVerilog( + instanceType, + instanceName, + ports, + ) ?? + SystemVerilogSynthesizer.instantiationVerilogFor( + module: module, + instanceType: instanceType, + instanceName: instanceName, + ports: ports, + forceStandardInstantiation: true, + ); + }), if (dumpWavesString != null) dumpWavesString, 'endmodule' ].join('\n'); From bfaa4c5ff3b6f6a7032a727f5470f9268484cd77 Mon Sep 17 00:00:00 2001 From: Max Korbel Date: Fri, 25 Apr 2025 15:49:30 -0700 Subject: [PATCH 3/3] fix def name --- lib/src/configs/cosim_wrap_config.dart | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/src/configs/cosim_wrap_config.dart b/lib/src/configs/cosim_wrap_config.dart index 51c80a1..d763151 100644 --- a/lib/src/configs/cosim_wrap_config.dart +++ b/lib/src/configs/cosim_wrap_config.dart @@ -141,9 +141,9 @@ class CosimWrapConfig extends CosimProcessConfig { final wrapperVerilog = [ 'module $_wrapperName();', ...registrees.entries.map((registreeEntry) { - const instanceType = 'dont_care'; final instanceName = registreeEntry.key; final module = registreeEntry.value; + final instanceType = module.definitionName; final ports = { ...registreeEntry.value.inputs, ...registreeEntry.value.outputs,