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Delete LinalgExt::PackOp and LinalgExt::UnPackOp
Signed-off-by: hanhanW <hanhan0912@gmail.com>
1 parent 272aee5 commit 6559bee

9 files changed

Lines changed: 1 addition & 2211 deletions

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‎compiler/src/iree/compiler/Codegen/Common/test/iree_comprehensive_bufferize.mlir‎

Lines changed: 0 additions & 140 deletions
Original file line numberDiff line numberDiff line change
@@ -2409,146 +2409,6 @@ func.func @topk() {
24092409

24102410
// -----
24112411

2412-
#pipeline_layout = #hal.pipeline.layout<bindings = [
2413-
#hal.pipeline.binding<storage_buffer>,
2414-
#hal.pipeline.binding<storage_buffer>
2415-
]>
2416-
func.func @iree_linalg_ext_pack() {
2417-
%c0 = arith.constant 0 : index
2418-
%c0_i32 = arith.constant 0 : i32
2419-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<4x4xi32>>
2420-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<2x2x3x3xi32>>
2421-
%2 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0, 0, 0], sizes = [2, 2, 3, 3], strides = [1, 1, 1, 1] : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<2x2x3x3xi32>> -> tensor<2x2x3x3xi32>
2422-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<4x4xi32>> -> tensor<4x4xi32>
2423-
%4 = iree_linalg_ext.pack %3 padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [3, 3] into %2 : (tensor<4x4xi32> tensor<2x2x3x3xi32>) -> tensor<2x2x3x3xi32>
2424-
iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [0, 0, 0, 0], sizes = [2, 2, 3, 3], strides = [1, 1, 1, 1] : tensor<2x2x3x3xi32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<2x2x3x3xi32>>
2425-
return
2426-
}
2427-
// CHECK: func.func @iree_linalg_ext_pack
2428-
// CHECK-DAG: %[[PAD:.+]] = arith.constant 0 : i32
2429-
// CHECK-DAG: %[[IN:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0) alignment(64) offset(%c0) : memref<4x4xi32, #hal.descriptor_type<storage_buffer>>
2430-
// CHECK-DAG: %[[OUT:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1) alignment(64) offset(%c0) : memref<2x2x3x3xi32, #hal.descriptor_type<storage_buffer>>
2431-
// CHECK: iree_linalg_ext.pack %[[IN]]
2432-
// CHECK-SAME: padding_value(%[[PAD]] : i32)
2433-
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [3, 3] into %[[OUT]]
2434-
2435-
// -----
2436-
2437-
#pipeline_layout = #hal.pipeline.layout<bindings = [
2438-
#hal.pipeline.binding<storage_buffer>,
2439-
#hal.pipeline.binding<storage_buffer>
2440-
]>
2441-
func.func @iree_linalg_ext_unpack() {
2442-
%c0 = arith.constant 0 : index
2443-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>>
2444-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2445-
%2 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>> -> tensor<4x4xi32>
2446-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0, 0, 0], sizes = [2, 2, 2, 2], strides = [1, 1, 1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>> -> tensor<2x2x2x2xi32>
2447-
%4 = iree_linalg_ext.unpack %3 inner_dims_pos = [0, 1] inner_tiles = [2, 2] into %2 : (tensor<2x2x2x2xi32> tensor<4x4xi32>) -> tensor<4x4xi32>
2448-
iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : tensor<4x4xi32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2449-
return
2450-
}
2451-
// CHECK: func.func @iree_linalg_ext_unpack
2452-
// CHECK-DAG: %[[IN:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0) alignment(64) offset(%c0) : memref<2x2x2x2xi32, #hal.descriptor_type<storage_buffer>>
2453-
// CHECK-DAG: %[[OUT:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1) alignment(64) offset(%c0) : memref<4x4xi32, #hal.descriptor_type<storage_buffer>>
2454-
// CHECK: iree_linalg_ext.unpack %[[IN]]
2455-
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [2, 2] into %[[OUT]]
2456-
2457-
// -----
2458-
2459-
#pipeline_layout = #hal.pipeline.layout<bindings = [
2460-
#hal.pipeline.binding<storage_buffer>,
2461-
#hal.pipeline.binding<storage_buffer>
2462-
]>
2463-
func.func @iree_linalg_ext_unpack_fully_dynamic() {
2464-
%c0 = arith.constant 0 : index
2465-
%inner_d0 = util.unfoldable_constant 2 : index
2466-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>>
2467-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2468-
%2 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>> -> tensor<4x4xi32>
2469-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0, 0, 0], sizes = [2, 2, %inner_d0, %inner_d0], strides = [1, 1, 1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>> -> tensor<2x2x?x?xi32>
2470-
%4 = iree_linalg_ext.unpack %3 inner_dims_pos = [0, 1] inner_tiles = [%inner_d0, %inner_d0] into %2 : (tensor<2x2x?x?xi32> tensor<4x4xi32>) -> tensor<4x4xi32>
2471-
iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : tensor<4x4xi32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2472-
return
2473-
}
2474-
2475-
// CHECK: func.func @iree_linalg_ext_unpack_fully_dynamic
2476-
// CHECK-DAG: %[[D:.+]] = util.optimization_barrier %c2 : index
2477-
// CHECK: iree_linalg_ext.unpack
2478-
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [%[[D]], %[[D]]]
2479-
2480-
// -----
2481-
2482-
#pipeline_layout = #hal.pipeline.layout<bindings = [
2483-
#hal.pipeline.binding<storage_buffer>,
2484-
#hal.pipeline.binding<storage_buffer>
2485-
]>
2486-
func.func @tensor_pack() {
2487-
%c0 = arith.constant 0 : index
2488-
%c0_i32 = arith.constant 0 : i32
2489-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<4x4xi32>>
2490-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<2x2x3x3xi32>>
2491-
%2 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0, 0, 0], sizes = [2, 2, 3, 3], strides = [1, 1, 1, 1] : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<2x2x3x3xi32>> -> tensor<2x2x3x3xi32>
2492-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<4x4xi32>> -> tensor<4x4xi32>
2493-
%4 = linalg.pack %3 padding_value(%c0_i32 : i32) inner_dims_pos = [0, 1] inner_tiles = [3, 3] into %2 : tensor<4x4xi32> -> tensor<2x2x3x3xi32>
2494-
iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [0, 0, 0, 0], sizes = [2, 2, 3, 3], strides = [1, 1, 1, 1] : tensor<2x2x3x3xi32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<2x2x3x3xi32>>
2495-
return
2496-
}
2497-
// CHECK: func.func @tensor_pack
2498-
// CHECK-DAG: %[[PAD:.+]] = arith.constant 0 : i32
2499-
// CHECK-DAG: %[[IN:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0) alignment(64) offset(%c0) : memref<4x4xi32, #hal.descriptor_type<storage_buffer>>
2500-
// CHECK-DAG: %[[OUT:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1) alignment(64) offset(%c0) : memref<2x2x3x3xi32, #hal.descriptor_type<storage_buffer>>
2501-
// CHECK: iree_linalg_ext.pack %[[IN]]
2502-
// CHECK-SAME: padding_value(%[[PAD]] : i32)
2503-
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [3, 3] into %[[OUT]]
2504-
2505-
// -----
2506-
2507-
#pipeline_layout = #hal.pipeline.layout<bindings = [
2508-
#hal.pipeline.binding<storage_buffer>,
2509-
#hal.pipeline.binding<storage_buffer>
2510-
]>
2511-
func.func @tensor_unpack() {
2512-
%c0 = arith.constant 0 : index
2513-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>>
2514-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2515-
%2 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>> -> tensor<4x4xi32>
2516-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0, 0, 0], sizes = [2, 2, 2, 2], strides = [1, 1, 1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>> -> tensor<2x2x2x2xi32>
2517-
%4 = linalg.unpack %3 inner_dims_pos = [0, 1] inner_tiles = [2, 2] into %2 : tensor<2x2x2x2xi32> -> tensor<4x4xi32>
2518-
iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : tensor<4x4xi32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2519-
return
2520-
}
2521-
// CHECK: func.func @tensor_unpack
2522-
// CHECK-DAG: %[[IN:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0) alignment(64) offset(%c0) : memref<2x2x2x2xi32, #hal.descriptor_type<storage_buffer>>
2523-
// CHECK-DAG: %[[OUT:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1) alignment(64) offset(%c0) : memref<4x4xi32, #hal.descriptor_type<storage_buffer>>
2524-
// CHECK: iree_linalg_ext.unpack %[[IN]]
2525-
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [2, 2] into %[[OUT]]
2526-
2527-
// -----
2528-
2529-
#pipeline_layout = #hal.pipeline.layout<bindings = [
2530-
#hal.pipeline.binding<storage_buffer>,
2531-
#hal.pipeline.binding<storage_buffer>
2532-
]>
2533-
func.func @tensor_unpack_fully_dynamic() {
2534-
%c0 = arith.constant 0 : index
2535-
%inner_d0 = util.unfoldable_constant 2 : index
2536-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>>
2537-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2538-
%2 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>> -> tensor<4x4xi32>
2539-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0, 0, 0], sizes = [2, 2, %inner_d0, %inner_d0], strides = [1, 1, 1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x2x2x2xi32>> -> tensor<2x2x?x?xi32>
2540-
%4 = linalg.unpack %3 inner_dims_pos = [0, 1] inner_tiles = [%inner_d0, %inner_d0] into %2 : tensor<2x2x?x?xi32> -> tensor<4x4xi32>
2541-
iree_tensor_ext.dispatch.tensor.store %4, %1, offsets = [0, 0], sizes = [4, 4], strides = [1, 1] : tensor<4x4xi32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<4x4xi32>>
2542-
return
2543-
}
2544-
2545-
// CHECK: func.func @tensor_unpack_fully_dynamic
2546-
// CHECK-DAG: %[[D:.+]] = util.optimization_barrier %c2 : index
2547-
// CHECK: iree_linalg_ext.unpack
2548-
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [%[[D]], %[[D]]]
2549-
2550-
// -----
2551-
25522412
#pipeline_layout = #hal.pipeline.layout<bindings = [
25532413
#hal.pipeline.binding<storage_buffer>,
25542414
#hal.pipeline.binding<storage_buffer>

‎compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.cpp‎

Lines changed: 0 additions & 166 deletions
Original file line numberDiff line numberDiff line change
@@ -383,157 +383,6 @@ struct LinalgExtOpInterfaceHelper {
383383
}
384384
};
385385

386-
/// Returns the buffers of the source and destination for pack and unpack ops.
387-
/// Returns a failure if the buffers can not be found.
388-
template <typename OpTy>
389-
static FailureOr<std::pair<Value, Value>>
390-
getSourceAndDestFromPackUnPackOp(RewriterBase &rewriter, OpTy op,
391-
const BufferizationOptions &options,
392-
const BufferizationState &state) {
393-
static_assert(llvm::is_one_of<OpTy, linalg::PackOp, linalg::UnPackOp>::value);
394-
Value source;
395-
auto maybeBuffer = getBuffer(rewriter, op.getSource(), options, state);
396-
if (failed(maybeBuffer)) {
397-
return failure();
398-
}
399-
source = *maybeBuffer;
400-
401-
Value dest;
402-
AnalysisState analysisState(options);
403-
AliasingOpOperandList aliasingOpOperands =
404-
analysisState.getAliasingOpOperands(op->getOpResult(0));
405-
assert(aliasingOpOperands.getNumAliases() == 1 && "expected 1 OpOperand");
406-
FailureOr<Value> resultBuffer = getBuffer(
407-
rewriter, aliasingOpOperands.getAliases().front().opOperand->get(),
408-
options, state);
409-
if (failed(resultBuffer)) {
410-
return failure();
411-
}
412-
dest = *resultBuffer;
413-
return std::make_pair(source, dest);
414-
}
415-
416-
static LogicalResult bufferizePackOp(RewriterBase &rewriter, linalg::PackOp op,
417-
const BufferizationOptions &options,
418-
const BufferizationState &state) {
419-
// Take a guard before anything else.
420-
OpBuilder::InsertionGuard g(rewriter);
421-
rewriter.setInsertionPoint(op);
422-
423-
auto maybeSrcAndDest =
424-
getSourceAndDestFromPackUnPackOp(rewriter, op, options, state);
425-
if (failed(maybeSrcAndDest)) {
426-
return failure();
427-
}
428-
auto [source, dest] = *maybeSrcAndDest;
429-
430-
// Set insertion point now that potential alloc/dealloc are introduced.
431-
rewriter.setInsertionPoint(op);
432-
IREE::LinalgExt::PackOp::create(rewriter, op.getLoc(), source, dest,
433-
op.getInnerDimsPos(), op.getMixedTiles(),
434-
op.getPaddingValue(), op.getOuterDimsPerm());
435-
436-
// Replace the results of the old op with the new output buffers.
437-
bufferization::replaceOpWithBufferizedValues(rewriter, op, dest);
438-
439-
return success();
440-
}
441-
442-
static LogicalResult bufferizeUnPackOp(RewriterBase &rewriter,
443-
linalg::UnPackOp op,
444-
const BufferizationOptions &options,
445-
const BufferizationState &state) {
446-
// Take a guard before anything else.
447-
OpBuilder::InsertionGuard g(rewriter);
448-
rewriter.setInsertionPoint(op);
449-
450-
auto maybeSrcAndDest =
451-
getSourceAndDestFromPackUnPackOp(rewriter, op, options, state);
452-
if (failed(maybeSrcAndDest)) {
453-
return failure();
454-
}
455-
auto [source, dest] = *maybeSrcAndDest;
456-
457-
// Set insertion point now that potential alloc/dealloc are introduced.
458-
rewriter.setInsertionPoint(op);
459-
IREE::LinalgExt::UnPackOp::create(rewriter, op.getLoc(), source, dest,
460-
op.getInnerDimsPos(), op.getMixedTiles(),
461-
op.getOuterDimsPerm());
462-
463-
// Replace the results of the old op with the new output buffers.
464-
bufferization::replaceOpWithBufferizedValues(rewriter, op, dest);
465-
466-
return success();
467-
}
468-
469-
template <typename OpTy>
470-
struct PackUnPackOpInterface
471-
: public BufferizableOpInterface::ExternalModel<PackUnPackOpInterface<OpTy>,
472-
OpTy> {
473-
bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
474-
const AnalysisState &state) const {
475-
return true;
476-
}
477-
478-
bool bufferizesToMemoryWrite(Operation *op, OpOperand &opOperand,
479-
const AnalysisState &state) const {
480-
// Operand is written to if it has an aliasing OpResult.
481-
auto dpsOp = cast<DestinationStyleOpInterface>(op);
482-
return dpsOp.isDpsInit(&opOperand);
483-
}
484-
485-
SmallVector<OpOperand *>
486-
getAliasingOpOperand(Operation *op, OpResult opResult,
487-
const AnalysisState &state) const {
488-
auto dpsOp = cast<DestinationStyleOpInterface>(op);
489-
return {dpsOp.getDpsInitOperand(opResult.getResultNumber())};
490-
}
491-
492-
SmallVector<OpResult> getAliasingValue(Operation *op, OpOperand &opOperand,
493-
const AnalysisState &state) const {
494-
auto dspOp = cast<DestinationStyleOpInterface>(op);
495-
496-
// The i-th "out" tensor may alias with the i-th OpResult.
497-
if (dspOp.isDpsInit(&opOperand)) {
498-
return {dspOp.getTiedOpResult(&opOperand)};
499-
}
500-
return {};
501-
}
502-
503-
bufferization::AliasingValueList
504-
getAliasingValues(Operation *op, OpOperand &opOperand,
505-
const AnalysisState &state) const {
506-
auto dspOp = cast<DestinationStyleOpInterface>(op);
507-
508-
// The i-th "out" tensor may alias with the i-th OpResult.
509-
if (dspOp.isDpsInit(&opOperand)) {
510-
return {AliasingValue(dspOp.getTiedOpResult(&opOperand),
511-
BufferRelation::Equivalent,
512-
/*isDefinite=*/false)};
513-
}
514-
return {};
515-
}
516-
517-
bufferization::BufferRelation
518-
bufferRelation(Operation *op, OpResult opResult,
519-
const AnalysisState &state) const {
520-
return bufferization::BufferRelation::Equivalent;
521-
}
522-
523-
LogicalResult bufferize(Operation *op, RewriterBase &rewriter,
524-
const BufferizationOptions &options,
525-
bufferization::BufferizationState &state) const {
526-
return TypeSwitch<Operation *, LogicalResult>(op)
527-
.Case([&](linalg::PackOp pack) {
528-
return bufferizePackOp(rewriter, pack, options, state);
529-
})
530-
.Case([&](linalg::UnPackOp unpack) {
531-
return bufferizeUnPackOp(rewriter, unpack, options, state);
532-
})
533-
.Default(failure());
534-
}
535-
};
536-
537386
struct DispatchTensorLoadOpSubsetInterface
538387
: public SubsetOpInterface::ExternalModel<
539388
DispatchTensorLoadOpSubsetInterface,
@@ -711,21 +560,6 @@ struct StoreToBufferOpSubsetInsertionInterface
711560
//===----------------------------------------------------------------------===//
712561

713562
void registerBufferizationInterfaces(DialectRegistry &registry) {
714-
// Prioritize IREE's PackOp/UnPackOp bufferization over the upstream's one.
715-
// These create IREE::LinalgExt::Pack/UnPackOp instead of keeping linalg ops.
716-
// This must be registered before the upstream linalg registration below,
717-
// because MLIR's attachInterface uses first-one-wins semantics.
718-
// The scalar code support (i.e., `generateScalarImplementation`) is not yet
719-
// upstreamed, so the lowering path is not working.
720-
// TODO(#20030): Remove once IREE's pack/unpack ops are fully upstreamed.
721-
// registry.insert<linalg::LinalgDialect>();
722-
// registry.addExtension(+[](MLIRContext *ctx, linalg::LinalgDialect *dialect) {
723-
// linalg::PackOp::attachInterface<PackUnPackOpInterface<linalg::PackOp>>(
724-
// *ctx);
725-
// linalg::UnPackOp::attachInterface<PackUnPackOpInterface<linalg::UnPackOp>>(
726-
// *ctx);
727-
// });
728-
729563
arith::registerBufferizableOpInterfaceExternalModels(registry);
730564
linalg::registerBufferizableOpInterfaceExternalModels(registry);
731565
scf::registerBufferizableOpInterfaceExternalModels(registry);

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