Yosys compat: need to include SystemVerilog reserved keywords in Reserved_words

[edwintorok]

I tried naming one of my signals "dist", but Yosys failed to parse the resulting file.

Looking at its source code it uses the SystemVerilog reserved word list, even when parsing regular Verilog: https://github.com/YosysHQ/yosys/blob/main/backends/verilog/verilog_backend.cc#L133-L155

I think it'd be better to update 'reserved_words.ml' and include the SystemVerilog list too.

If you want I can send a PR that does that.

[andrewray]

Thanks for the report.

I've imported the systemverilog keywords and will consider how to integrate them.

I'd like to make an internal plumbing change in hardcaml related to name mangling which would make it easier to specify a "custom" keyword list. But if that refactor starts to look difficult I'll switch the verilog generator over to use systemverilog keywords as an interim measure.

I'll keep this issue open until I have done one or the other fix.