degu tracing update, but still sensitive to timing

jeras · jeras · commit 7d8f47177160 · 2025-11-25T14:21:59.000+01:00
diff --git a/hdl/tbn/riscof/r5p_degu_riscof_tb.sv b/hdl/tbn/riscof/r5p_degu_riscof_tb.sv
@@ -268,9 +268,10 @@ module r5p_degu_riscof_tb
     ) trace_hdldb (
         // GPR register file array
         // hierarchical path to GPR inside RTL
-        .gpr_wen  (dut.gpr.e_rd),
-        .gpr_wid  (dut.gpr.a_rd),
-        .gpr_wdt  (dut.gpr.d_rd),
+        .gpr_den  (dut.gpr.e_rd),
+        .gpr_did  (dut.gpr.a_rd),
+        .gpr_ddt  (dut.gpr.d_rd),
+        .gpr_sid  (dut.gpr.a_rs1),
         // TCB IFU/LSU system busses
         .tcb_ifu  (tcb_ifu),
         .tcb_lsu  (tcb_lsu)
diff --git a/hdl/tbn/riscof/r5p_mouse_riscof_tb.sv b/hdl/tbn/riscof/r5p_mouse_riscof_tb.sv
@@ -242,7 +242,6 @@ import riscv_asm_pkg::*;
 
     // trace with Spike format
     r5p_mouse_trace #(
-        .XLEN   (XLEN),
         .FORMAT (format)
     ) trace_hdldb (
         // instruction execution phase
diff --git a/hdl/tbn/riscof/trace_spike_pkg.sv b/hdl/tbn/riscof/trace_spike_pkg.sv
@@ -58,33 +58,42 @@ package trace_spike_pkg;
         function void trace (
             int unsigned     core,     // core (hart) index
             // IFU
-            logic [XLEN-1:0] ifu_adr,  // PC (IFU address)
-            logic [XLEN-1:0] ifu_ins,  // instruction
+            logic [XLEN-1:0] ifu_adr,         // PC (IFU address)
+            logic            ifu_siz,         // instruction size (0-16bit, 1-32bit)
+            logic [XLEN-1:0] ifu_ins,         // instruction
+            logic            ifu_ill,         // instruction is illegal
             // WBU (write back to destination register)
-            logic            wbu_ena,  // enable
-            logic [   5-1:0] wbu_idx,  // index of destination register
-            logic [XLEN-1:0] wbu_dat,  // data
-            // LSU
-            logic            lsu_ena,  // enable
-            logic            lsu_wen,  // write enable
-            logic            lsu_ren,  // read enable
-            logic [XLEN-1:0] lsu_adr,  // PC (IFU address)
-            logic [XLEN-1:0] lsu_siz,  // load/store size
-            logic [XLEN-1:0] lsu_wdt   // write data (store)
+            logic            wbu_ena,         // enable
+            logic [   5-1:0] wbu_idx,         // index of destination register
+            logic [XLEN-1:0] wbu_dat,         // data
+            // LSU (load/store unit)
+            logic            lsu_ena,         // enable
+            logic            lsu_wen,         // write enable
+            logic            lsu_ren,         // read enable
+            logic [   5-1:0] lsu_wid,         // index of data source GPR
+            logic [   5-1:0] lsu_rid,         // index of data destination GPR
+            logic [XLEN-1:0] lsu_adr,         // PC (IFU address)
+            logic [   2-1:0] lsu_siz,         // load/store logarithmic size
+            logic [XLEN-1:0] lsu_wdt,         // write data (store)
+            logic [XLEN-1:0] lsu_rdt          // read data (load)
         );
             string str_if;  // instruction fetch
             string str_wb;  // write-back
             string str_ls;  // load/store
 
-            // prepare fetch
-            // TODO: add handling of compressed instructions
+            // fetch address
             case (XLEN)
-                32: str_if = $sformatf(" 0x%8h (0x%8h)" , ifu_adr, ifu_ins);
-                64: str_if = $sformatf(" 0x%16h (0x%8h)", ifu_adr, ifu_ins);
+                32: str_if = $sformatf(" 0x%8h" , ifu_adr);
+                64: str_if = $sformatf(" 0x%16h", ifu_adr);
+            endcase
+            // fetch instruction
+            case (ifu_siz)
+                0: str_if = {str_if, $sformatf(" (0x%4h)", ifu_ins[16-1:0])};  // 16bit
+                1: str_if = {str_if, $sformatf(" (0x%8h)", ifu_ins[32-1:0])};  // 32bit
             endcase
 
-            // prepare write-back
-            if (wbu_ena) begin
+            // write-back (x0 access is not logged)
+            if (wbu_ena && (wbu_idx != 0)) begin
                 case (XLEN)
                     32: str_wb = $sformatf(" %s 0x%8h" , format_gpr(wbu_idx), wbu_dat);
                     64: str_wb = $sformatf(" %s 0x%16h", format_gpr(wbu_idx), wbu_dat);
@@ -93,12 +102,16 @@ package trace_spike_pkg;
                 str_wb = "";
             end
 
-            // prepare load/store
+            // load/store
             if (lsu_ena) begin
-                case (XLEN)
-                    32: str_ls = $sformatf(" mem 0x%8h" , lsu_adr);
-                    64: str_ls = $sformatf(" mem 0x%16h", lsu_adr);
-                endcase
+                // load/store address
+                if (lsu_wen | lsu_wen) begin
+                    case (XLEN)
+                        32: str_ls = $sformatf(" mem 0x%8h" , lsu_adr);
+                        64: str_ls = $sformatf(" mem 0x%16h", lsu_adr);
+                    endcase
+                end
+                // store data
                 if (lsu_wen) begin
                     case (lsu_siz)
                         2'd0: str_ls = {str_ls, $sformatf(" 0x%2h" , lsu_wdt[ 8-1:0])};
diff --git a/hdl/tbn/soc/r5p_degu_trace.sv b/hdl/tbn/soc/r5p_degu_trace.sv
@@ -19,9 +19,12 @@
 module r5p_degu_trace
     import tcb_pkg::*;
     import trace_spike_pkg::*;
+    import riscv_isa_pkg::*;
+    import riscv_isa_i_pkg::*;
+//    import riscv_asm_pkg::*;
 #(
     // constants used across the design in signal range sizing instead of literals
-    localparam int unsigned XLEN = 32,
+    parameter  int unsigned XLEN = 32,
     localparam int unsigned XLOG = $clog2(XLEN),
     // trace format class type (HDLDB, Spike, ...)
     parameter type FORMAT = trace_spike_pkg::spike,
@@ -32,25 +35,23 @@ module r5p_degu_trace
     localparam int unsigned GLOG = $clog2(GNUM)
 )(
     // GPR array
-    input logic            gpr_wen,
-    input logic [GLOG-1:0] gpr_wid,
-    input logic [XLEN-1:0] gpr_wdt,
+    input logic            gpr_den,  // destination enable
+    input logic [GLOG-1:0] gpr_did,  // destination index
+    input logic [XLEN-1:0] gpr_ddt,  // destination data
+    input logic [GLOG-1:0] gpr_sid,  // source index
     // TCB IFU/LSU system busses
     tcb_if.mon tcb_ifu,
     tcb_if.mon tcb_lsu
 );
 
-//    import riscv_isa_pkg::*;
-//    import riscv_isa_i_pkg::*;
-//    import riscv_asm_pkg::*;
-
 ////////////////////////////////////////////////////////////////////////////////
 // local signals
 ////////////////////////////////////////////////////////////////////////////////
 
     // IFU (instruction fetch unit)
     logic            ifu_ena = 1'b0;  // enable
     logic [XLEN-1:0] ifu_adr;         // PC (IFU address)
+    logic            ifu_siz;         // instruction size (0-16bit, 1-32bit)
     logic [XLEN-1:0] ifu_ins;         // instruction
     logic            ifu_ill;         // instruction is illegal
     // WBU (write back to destination register)
@@ -64,10 +65,16 @@ module r5p_degu_trace
     logic [   5-1:0] lsu_wid;         // index of data source GPR
     logic [   5-1:0] lsu_rid;         // index of data destination GPR
     logic [XLEN-1:0] lsu_adr;         // PC (IFU address)
-    logic [XLEN-1:0] lsu_siz;         // load/store size
+    logic [   2-1:0] lsu_siz;         // load/store logarithmic size
     logic [XLEN-1:0] lsu_wdt;         // write data (store)
     logic [XLEN-1:0] lsu_rdt;         // read data (load)
 
+    // instruction pipeline
+    logic [XLEN-1:0] ifp_adr;         // PC (IFU address)
+    logic            ifp_siz;         // instruction size (0-16bit, 1-32bit)
+    logic [XLEN-1:0] ifp_ins;         // instruction
+    logic            ifp_ill;         // instruction is illegal
+
 ////////////////////////////////////////////////////////////////////////////////
 // tracing
 ////////////////////////////////////////////////////////////////////////////////
@@ -86,78 +93,54 @@ module r5p_degu_trace
         else if (FILE) begin
             filename = FILE;
         end
-        if (filename) begin
-            tracer = new(filename);
-            $display("TRACING: opened trace file: '%s'.", filename);
-        end else begin
-            $display("TRACING: no trace file name was provided.");
-        end
+        // initialize tracing object
+        tracer = new(filename);
     end
   
     final
     begin
         tracer.close();
     end
 
-    // initialize dummy data into the queue to enforce order
-    initial
-    begin
-      str_gpr = '{};
-      str_lsu = '{};
-      str_ifu = '{""};
-    end
-
-    // instruction fetch
+    // instruction pipeline
     always_ff @(posedge tcb_ifu.clk)
-    begin
-        if ($past(tcb_ifu.trn)) begin
-            if (opsiz(tcb_ifu.rsp.rdt) == 4) begin
-                str_ifu.push_front($sformatf(" 0x%8h (0x%8h)", $past(tcb_ifu.req.adr), tcb_ifu.rsp.rdt));
-            end else begin
-                str_ifu.push_front($sformatf(" 0x%8h (0x%4h)", $past(tcb_ifu.req.adr), tcb_ifu.rsp.rdt[16-1:0]));
-            end
-        end
+    if ($past(tcb_ifu.trn, 1)) begin
+        ifu_ena <= 1'b0;  // enable
+        ifp_adr <= $past(tcb_ifu.req.adr);
+        ifp_siz <= opsiz(tcb_ifu.rsp.rdt) == 4;
+        ifp_ins <=       tcb_ifu.rsp.rdt ;
+        ifp_ill <= 1'b0;  // TODO
     end
 
-    // GPR write-back (rs1/rs2 reads are not logged)
+    // instruction fetch
     always_ff @(posedge tcb_ifu.clk)
     begin
-      if ($past(tcb_ifu.trn)) begin
-        if (gpr_wen) begin
-          // ignore GPR x0
-          if (gpr_wid != 0) begin
-              str_gpr.push_front($sformatf(" %s 0x%8h", format_gpr(gpr_wid), gpr_wdt));
-          end
-        end else begin
-          str_gpr.push_front("");
-        end
-      end
-    end
-
-    // memory load/store
-    always_ff @(posedge tcb_lsu.clk)
-    begin
-      if ($past(tcb_lsu.trn)) begin
-        if ($past(tcb_lsu.req.wen)) begin
-          // memory store
-          str_lsu.push_front($sformatf(" mem 0x%8h 0x%8h", $past(tcb_lsu.req.adr), $past(tcb_lsu.req.wdt)));
-        end else begin
-          // memory load
-          str_lsu.push_front($sformatf(" 0x%8h (0x%8h)", $past(tcb_lsu.req.adr), tcb_lsu.rsp.rdt));
-        end
-      end
-    end
+        if ($past(tcb_ifu.trn, 2)) begin
+//            $display("DEBUG: fetch");
+            tracer.trace(
+                .core (0),
+                // IFU
+                .ifu_adr (ifp_adr),
+                .ifu_siz (ifp_siz),
+                .ifu_ins (ifp_ins),
+                .ifu_ill (ifp_ill),
+                // WBU (write back to destination register)
+                .wbu_ena (gpr_den),
+                .wbu_idx (gpr_did),
+                .wbu_dat (gpr_ddt),
+                // LSU
+                .lsu_ena ($past(tcb_lsu.trn    )),
+                .lsu_wen ($past(tcb_lsu.req.wen)),
+                .lsu_ren ($past(tcb_lsu.req.ren)),
+                .lsu_wid ($past(gpr_sid)),
+                .lsu_rid (      gpr_did),
+                .lsu_adr ($past(tcb_lsu.req.adr)),
+                .lsu_siz ($past(tcb_lsu.req.siz)),
+                .lsu_wdt ($past(tcb_lsu.req.wdt)),
+                .lsu_rdt (      tcb_lsu.rsp.rdt )
+            );
 
-    // prepare string for committed instruction
-    always_ff @(posedge tcb_ifu.clk)
-    begin
-      // only log if a log file was opened
-      if (fd) begin
-        // at instruction fetch combine strings from previous instructions
-        if ($past(tcb_ifu.trn)) begin
-          $fwrite(fd, "core   0: 3%s%s%s\n", str_ifu.pop_back(), str_gpr.pop_back(), str_lsu.pop_back());
         end
-      end
     end
 
 endmodule: r5p_degu_trace
diff --git a/hdl/tbn/soc/r5p_mouse_trace.sv b/hdl/tbn/soc/r5p_mouse_trace.sv
@@ -57,6 +57,7 @@ module r5p_mouse_trace
     // IFU (instruction fetch unit)
     logic            ifu_ena = 1'b0;  // enable
     logic [XLEN-1:0] ifu_adr;         // PC (IFU address)
+    logic            ifu_siz;         // instruction size (0-16bit, 1-32bit)
     logic [XLEN-1:0] ifu_ins;         // instruction
     logic            ifu_ill;         // instruction is illegal
     // WBU (write back to destination register)
@@ -70,7 +71,7 @@ module r5p_mouse_trace
     logic [   5-1:0] lsu_wid;         // index of data source GPR
     logic [   5-1:0] lsu_rid;         // index of data destination GPR
     logic [XLEN-1:0] lsu_adr;         // PC (IFU address)
-    logic [XLEN-1:0] lsu_siz;         // load/store size
+    logic [   2-1:0] lsu_siz;         // load/store logarithmic size
     logic [XLEN-1:0] lsu_wdt;         // write data (store)
     logic [XLEN-1:0] lsu_rdt;         // read data (load)
 
@@ -92,12 +93,8 @@ module r5p_mouse_trace
         else if (FILE) begin
             filename = FILE;
         end
-        if (filename) begin
-            tracer = new(filename);
-            $display("TRACING: opened trace file: '%s'.", filename);
-        end else begin
-            $display("TRACING: no trace file name was provided.");
-        end
+        // initialize tracing object
+        tracer = new(filename);
     end
   
     final
@@ -118,7 +115,9 @@ module r5p_mouse_trace
                         .core (0),
                         // IFU
                         .ifu_adr (ifu_adr),
+                        .ifu_siz (      1),
                         .ifu_ins (ifu_ins),
+                        .ifu_ill (ifu_ill),
                         // WBU (write back to destination register)
                         .wbu_ena (wbu_ena),
                         .wbu_idx (wbu_idx),
@@ -127,9 +126,12 @@ module r5p_mouse_trace
                         .lsu_ena (lsu_ena),
                         .lsu_wen (lsu_wen),
                         .lsu_ren (lsu_ren),
+                        .lsu_wid ('x),
+                        .lsu_rid ('x),
                         .lsu_adr (lsu_adr),
                         .lsu_siz (lsu_siz),
-                        .lsu_wdt (lsu_wdt)
+                        .lsu_wdt (lsu_wdt),
+                        .lsu_rdt (lsu_rdt)
                     );
                 end
                 // instruction fetch
diff --git a/sim/sources-degu.mk b/sim/sources-degu.mk
@@ -30,7 +30,7 @@ TSV+=${PATH_TCB}/tbn/vip/tcb_vip_protocol_checker.sv
 PATH_GDB=../../submodules/hdldb/hdl
 
 # SystemVerilog bench (Test SV)
-TSV+=${PATH_GDB}/hdldb_trace_pkg.sv
+#TSV+=${PATH_GDB}/hdldb_trace_pkg.sv
 
 # R5P files
 PATH_R5P=../../hdl
@@ -64,11 +64,11 @@ RTL+=${PATH_R5P}/rtl/soc/r5p_degu_soc_top.sv
 
 # SystemVerilog bench (Test SV)
 TSV+=${PATH_R5P}/tbn/riscv/riscv_asm_pkg.sv
+TSV+=${PATH_R5P}/tbn/soc/r5p_degu_trace.sv
+TSV+=${PATH_R5P}/tbn/soc/r5p_degu_soc_top_tb.sv
 TSV+=${PATH_R5P}/tbn/htif/r5p_htif.sv
-TSV+=${PATH_R5P}/tbn/riscof/r5p_degu_trace_spike.sv
+TSV+=${PATH_R5P}/tbn/riscof/trace_spike_pkg.sv
 TSV+=${PATH_R5P}/tbn/riscof/r5p_degu_riscof_tb.sv
-TSV+=${PATH_R5P}/tbn/soc/r5p_degu_trace_hdldb.sv
-TSV+=${PATH_R5P}/tbn/soc/r5p_degu_soc_top_tb.sv
 
 # combined HDL sources
 HDL =${RTL}
