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jerasjeras
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2 files changed

+146
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‎hdl/tbn/riscof/trace_spike.sv‎ renamed to ‎hdl/tbn/riscof/trace_spike_pkg.sv‎

Lines changed: 36 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -16,14 +16,11 @@
1616
// limitations under the License.
1717
///////////////////////////////////////////////////////////////////////////////
1818

19-
module trace_spike_pkg
19+
package trace_spike_pkg;
2020
import riscv_isa_pkg::*;
2121
import riscv_isa_i_pkg::*;
22-
#(
23-
parameter int unsigned XLEN = 32
24-
// trace file name
25-
parameter string FILE = ""
26-
);
22+
23+
parameter int unsigned XLEN = 32;
2724

2825
////////////////////////////////////////////////////////////////////////////////
2926
// tracing (matching spike simulator logs)
@@ -36,62 +33,58 @@ module trace_spike_pkg
3633
endfunction: format_gpr
3734

3835
// prepare string for committed instruction
39-
function void trace (
36+
function string trace (
37+
int unsigned core, // core (hart) index
4038
// IFU
4139
logic [XLEN-1:0] ifu_adr, // PC (IFU address)
4240
logic [XLEN-1:0] ifu_ins, // instruction
41+
logic ifu_ill, // instruction is illegal
4342
// WBU (write back to destination register)
44-
logic [ 5-1:0] wbu_idx, // index
43+
logic wbu_vld, // valid
44+
logic [ 5-1:0] wbu_idx, // index of destination register
4545
logic [XLEN-1:0] wbu_dat, // data
4646
// LSU
47+
logic lsu_vld, // valid
48+
logic lsu_wen, // enable
49+
logic [ 5-1:0] lsu_idx, // index of data source register
4750
logic [XLEN-1:0] lsu_adr, // PC (IFU address)
48-
logic [XLEN-1:0] lsu_siz, // PC (IFU address)
49-
logic [XLEN-1:0] lsu_wdt, // instruction
50-
logic [XLEN-1:0] lsu_rdt, // instruction
51+
logic [XLEN-1:0] lsu_siz, // load/store size
52+
logic [XLEN-1:0] lsu_wdt, // write data (store)
53+
logic [XLEN-1:0] lsu_rdt // read data (load)
5154
);
52-
string str_if;
53-
string str_wb;
54-
string str_ld;
55-
string str_st;
55+
string str_if; // instruction fetch
56+
string str_wb; // write-back
57+
string str_ld; // load
58+
string str_st; // store
59+
string str_ls; // load/store
60+
61+
// prepare fetch
5662
str_if = $sformatf(" 0x%8h (0x%8h)", ifu_adr, ifu_ins);
57-
str_wb = $sformatf(" %s 0x%8h", format_gpr(wbu_idx), wbu_dat);
58-
str_ld = $sformatf(" mem 0x%8h", $past(tcb.req.adr));
63+
64+
// prepare write-back
65+
str_wb = wbu_vld ? $sformatf(" %s 0x%8h", format_gpr(wbu_idx), wbu_dat) : "";
66+
67+
// prepare load
68+
str_ld = $sformatf(" mem 0x%8h", lsu_adr);
69+
70+
// prepare store
5971
case (lsu_siz)
6072
2'd0: str_st = $sformatf(" mem 0x%8h 0x%2h", lsu_adr, lsu_wdt[ 8-1:0]);
6173
2'd1: str_st = $sformatf(" mem 0x%8h 0x%4h", lsu_adr, lsu_wdt[16-1:0]);
6274
2'd2: str_st = $sformatf(" mem 0x%8h 0x%8h", lsu_adr, lsu_wdt[32-1:0]);
6375
// 2'd3: str_st = $sformatf(" mem 0x%8h 0x%16h", lsu_adr, lsu_wdt[64-1:0]);
76+
default: $error("Unsupported store size %0d", lsu_siz);
6477
endcase
6578

66-
$fwrite(fd, "core 0: 3%s%s%s%s\n", str_if, str_wb, str_ld, str_st);
79+
// prepare load/store
80+
str_ls = lsu_vld ? (lsu_wen ? str_st : str_ld) : "";
81+
82+
// combine fetch/write-back/load/store
83+
return($sformatf("core %0d: 3%s%s%s%s\n", core, str_if, str_wb, str_ld, str_st));
6784
endfunction: trace
68-
69-
// open trace file if name is given by parameter
70-
initial
71-
begin
72-
// trace file if name is given by parameter
73-
if ($value$plusargs("trace=%s", fn)) begin
74-
end
75-
// trace file with filename obtained through plusargs
76-
else if (FILE) begin
77-
fn = FILE;
78-
end
79-
if (fn) begin
80-
fd = $fopen(fn, "w");
81-
$display("TRACING: opened trace file: '%s'.", fn);
82-
end else begin
83-
$display("TRACING: no trace file name was provided.");
84-
end
85-
end
86-
87-
final
88-
begin
89-
$fclose(fd);
90-
$display("TRACING: closed trace file: '%s'.", fn);
91-
end
9285

9386
////////////////////////////////////////////////////////////////////////////////
9487
// statistics
9588
////////////////////////////////////////////////////////////////////////////////
9689

97-
endmodule: trace_spike
90+
endpackage: trace_spike_pkg

‎hdl/tbn/soc/r5p_mouse_trace.sv‎

Lines changed: 110 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -17,82 +17,132 @@
1717
///////////////////////////////////////////////////////////////////////////////
1818

1919
module r5p_mouse_trace
20-
import riscv_isa_pkg::*;
21-
import riscv_isa_i_pkg::*;
22-
import tcb_pkg::*;
20+
import tcb_pkg::*;
2321
#(
24-
// trace file name
25-
string FILE = ""
22+
// trace file name
23+
string FILE = ""
2624
)(
27-
// instruction execution phase
28-
input logic [3-1:0] pha,
29-
// TCB system bus
30-
tcb_if.mon tcb
25+
// instruction execution phase
26+
input logic [3-1:0] pha,
27+
// TCB system bus
28+
tcb_if.mon tcb
3129
);
3230

31+
import riscv_isa_pkg::*;
32+
import riscv_isa_i_pkg::*;
33+
import riscv_asm_pkg::*;
34+
import trace_spike_pkg;
35+
3336
////////////////////////////////////////////////////////////////////////////////
34-
// local parameters and signals
37+
// local parameters
3538
////////////////////////////////////////////////////////////////////////////////
3639

37-
import riscv_asm_pkg::*;
38-
import tcb_pkg::*;
39-
40-
// TODO: try to share this table with RTL, while keeping Verilog2005 compatibility ?
41-
// FSM phases (GPR access phases can be decoded from a single bit)
42-
localparam logic [3-1:0] IF = 3'b000; // instruction fetch
43-
localparam logic [3-1:0] RS1 = 3'b101; // read register source 1
44-
localparam logic [3-1:0] RS2 = 3'b110; // read register source 1
45-
localparam logic [3-1:0] MLD = 3'b001; // memory load
46-
localparam logic [3-1:0] MST = 3'b010; // memory store
47-
localparam logic [3-1:0] EXE = 3'b011; // execute (only used to evaluate branching condition)
48-
localparam logic [3-1:0] WB = 3'b100; // GPR write-back
40+
// TODO: try to share this table with RTL, while keeping Verilog2005 compatibility ?
41+
// FSM phases (GPR access phases can be decoded from a single bit)
42+
localparam logic [3-1:0] IF = 3'b000; // instruction fetch
43+
localparam logic [3-1:0] RS1 = 3'b101; // read register source 1
44+
localparam logic [3-1:0] RS2 = 3'b110; // read register source 1
45+
localparam logic [3-1:0] MLD = 3'b001; // memory load
46+
localparam logic [3-1:0] MST = 3'b010; // memory store
47+
localparam logic [3-1:0] EXE = 3'b011; // execute (only used to evaluate branching condition)
48+
localparam logic [3-1:0] WB = 3'b100; // GPR write-back
4949

50-
// trace file name and descriptor
51-
string fn; // file name
52-
int fd;
50+
////////////////////////////////////////////////////////////////////////////////
51+
// local signals
52+
////////////////////////////////////////////////////////////////////////////////
5353

54-
// print-out delay queue
55-
string str_if [$]; // instruction fetch
56-
string str_wb [$]; // GPR write-back
57-
string str_ld [$]; // load
58-
string str_st [$]; // store
54+
// IFU
55+
logic ifu_vld; // valid
56+
logic [XLEN-1:0] ifu_adr; // PC (IFU address)
57+
logic [XLEN-1:0] ifu_ins; // instruction
58+
logic ifu_ill; // instruction is illegal
59+
// WBU (write back to destination register)
60+
logic wbu_vld; // valid
61+
logic [ 5-1:0] wbu_idx; // index of destination register
62+
logic [XLEN-1:0] wbu_dat; // data
63+
// LSU
64+
logic lsu_vld; // valid
65+
logic lsu_wen; // enable
66+
logic [ 5-1:0] lsu_idx; // index of data source register
67+
logic [XLEN-1:0] lsu_adr; // PC (IFU address)
68+
logic [XLEN-1:0] lsu_siz; // load/store size
69+
logic [XLEN-1:0] lsu_wdt; // write data (store)
70+
logic [XLEN-1:0] lsu_rdt; // read data (load)
5971

6072
////////////////////////////////////////////////////////////////////////////////
61-
// tracing (matching spike simulator logs)
73+
// tracing
6274
////////////////////////////////////////////////////////////////////////////////
6375

64-
// format GPR string with desired whitespace
65-
function string format_gpr (logic [5-1:0] idx);
66-
if (idx < 10) return($sformatf("x%0d ", idx));
67-
else return($sformatf("x%0d", idx));
68-
endfunction: format_gpr
76+
initial begin
77+
ifu_vld = 1'b0;
78+
end
6979

70-
// prepare string for each execution phase
71-
always_ff @(posedge tcb.clk)
72-
begin
73-
if ($past(tcb.trn)) begin
74-
// instruction fetch
75-
if ($past(pha) == IF) begin
76-
str_if.push_front($sformatf(" 0x%8h (0x%8h)", $past(tcb.req.adr), tcb.rsp.rdt));
77-
end
78-
// GPR write-back (rs1/rs2 reads are not logged)
79-
if ($past(pha) == WB) begin
80-
str_wb.push_front($sformatf(" %s 0x%8h", format_gpr($past(tcb.req.adr[2+:5])), $past(tcb.req.wdt)));
81-
end
82-
// memory load
83-
if ($past(pha) == MLD) begin
84-
str_ld.push_front($sformatf(" mem 0x%8h", $past(tcb.req.adr)));
85-
end
86-
// memory store
87-
if ($past(pha) == MST) begin
88-
case ($past(tcb.req.siz))
89-
2'd0: str_st.push_front($sformatf(" mem 0x%8h 0x%2h", $past(tcb.req.adr), $past(tcb.req.wdt[ 8-1:0])));
90-
2'd1: str_st.push_front($sformatf(" mem 0x%8h 0x%4h", $past(tcb.req.adr), $past(tcb.req.wdt[16-1:0])));
91-
2'd2: str_st.push_front($sformatf(" mem 0x%8h 0x%8h", $past(tcb.req.adr), $past(tcb.req.wdt[32-1:0])));
80+
// prepare string for each execution phase
81+
always_ff @(posedge tcb.clk)
82+
if (tcb.rst) begin
83+
ifu_vld = 1'b0;
84+
end else if ($past(tcb.trn)) begin
85+
case ($past(pha))
86+
IF: begin
87+
// log instruction trace
88+
if (ifu_vld) begin
89+
string str = trace_spike::trace(
90+
.core (0),
91+
// IFU
92+
.ifu_adr,
93+
.ifu_ins,
94+
.ifu_ill,
95+
// WBU (write back to destination register)
96+
.wbu_vld,
97+
.wbu_idx,
98+
.wbu_dat,
99+
// LSU
100+
.lsu_vld,
101+
.lsu_wen,
102+
.lsu_idx,
103+
.lsu_adr,
104+
.lsu_siz,
105+
.lsu_wdt,
106+
.lsu_rdt
107+
);
108+
$fwrite(fd, str);
109+
end
110+
// instruction fetch
111+
ifu_vld <= 1'b1;
112+
ifu_adr <= $past(tcb.req.adr);
113+
ifu_ins <= tcb.rsp.rdt ;
114+
ifu_ill <= 1'b0; // TODO;
115+
// clear write-back/load/store valid
116+
wbu_vld <= 1'b0;
117+
lsu_vld <= 1'b0;
118+
end
119+
WB: begin
120+
// GPR write-back (rs1/rs2 reads are not logged)
121+
wbu_vld <= 1'b1;
122+
wbu_idx <= $past(tcb.req.adr[2+:5]);
123+
wbu_dat <= $past(tcb.req.wdt);
124+
end
125+
MLD: begin
126+
// memory load
127+
lsu_vld <= 1'b1;
128+
lsu_wen <= 1'b0; // read access
129+
lsu_idx <= 'x; // destination register is defined with `wbu_idx`
130+
lsu_adr <= $past(tcb.req.adr);
131+
lsu_siz <= $past(tcb.req.siz);
132+
lsu_rdt <= tcb.req.rdt ;
133+
end
134+
MST: begin
135+
// memory store
136+
lsu_vld <= 1'b1;
137+
lsu_wen <= 1'b0; // read access
138+
lsu_idx <= 'x; // destination register is defined with `wbu_idx`
139+
lsu_adr <= $past(tcb.req.adr);
140+
lsu_siz <= $past(tcb.req.siz);
141+
lsu_wdt <= $past(tcb.req.wdt);
142+
lsu_rdt <= tcb.req.rdt ;
143+
end
92144
endcase
93-
end
94145
end
95-
end
96146

97147
// prepare string for committed instruction
98148
always_ff @(posedge tcb.clk)
@@ -105,7 +155,6 @@ module r5p_mouse_trace
105155
if ($past(pha) == IF) begin
106156
// skip first fetch
107157
if (~$past(tcb.rst,3)) begin
108-
$fwrite(fd, "core 0: 3%s%s%s%s\n", str_if.pop_back(), str_wb.pop_back(), str_ld.pop_back(), str_st.pop_back());
109158
end
110159
end
111160
end

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