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arm-bsp/trusted-firmware-a: corstone1000: Multicore support for Corstone-1000 FVP
This changeset adds the multicore support in trusted-firmware-a for the Corstone-1000 FVP. Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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‎meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch‎

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From bd975fbcff8886b3d3ed3268d7b6fa41bd7fba2d Mon Sep 17 00:00:00 2001
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From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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Date: Thu, 9 May 2024 16:59:34 +0000
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Subject: [PATCH] feat(corstone1000): add multicore support for fvp
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This changeset adds the multicore support for the Corstone-1000 FVP.
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It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
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for the secondary cores.
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Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29176]
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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---
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.../common/corstone1000_helpers.S | 26 +++++++++++
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.../corstone1000/common/corstone1000_pm.c | 43 ++++++++++++++++++-
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.../common/include/platform_def.h | 15 ++++++-
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plat/arm/board/corstone1000/platform.mk | 8 ++++
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4 files changed, 90 insertions(+), 2 deletions(-)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
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index cbe27c3b5..90dc4fee6 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S
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+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
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@@ -21,8 +21,34 @@
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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+#if defined(CORSTONE1000_FVP_MULTICORE)
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+
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+ /* Calculate the address of our hold entry */
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+ bl plat_my_core_pos
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+ lsl x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT
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+ mov_imm x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE
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+
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+ /* Set the wait state for the secondary core */
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+ mov_imm x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT
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+ str x3, [x2, x0]
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+ dmb ish
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+
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+ /* Poll until the primary core signals to go */
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+poll_mailbox:
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+ ldr x1, [x2, x0]
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+ cmp x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT
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+ beq 1f
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+ mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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+ ldr x1, [x0]
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+ br x1
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+1:
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+ wfe
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+ b poll_mailbox
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+#else
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cb_panic:
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b cb_panic
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+#endif
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+
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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index 4b0a791e7..9cd384e18 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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@@ -24,10 +24,51 @@ static void __dead2 corstone1000_system_reset(void)
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wfi();
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}
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}
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+#if defined(CORSTONE1000_FVP_MULTICORE)
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+int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint)
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+{
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+ /*
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+ * Check if the non secure entrypoint lies within the non
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+ * secure DRAM.
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+ */
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+ if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
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+ return PSCI_E_SUCCESS;
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+ }
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+ return PSCI_E_INVALID_ADDRESS;
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+}
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+
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+int corstone1000_pwr_domain_on(u_register_t mpidr)
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+{
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+ int core_index = plat_core_pos_by_mpidr(mpidr);
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+ uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE;
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+
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+ /* Validate the core index */
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+ if ((core_index < 0) || (core_index > PLATFORM_CORE_COUNT)) {
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+ return PSCI_E_INVALID_PARAMS;
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+ }
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+ secondary_core_hold_base[core_index] = CORSTONE1000_SECONDARY_CORE_STATE_GO;
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+ dsbish();
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+ sev();
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+
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+ return PSCI_E_SUCCESS;
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+}
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+void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
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+{
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+ (void)target_state;
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+ plat_arm_gic_init();
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+}
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+#endif
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plat_psci_ops_t plat_arm_psci_pm_ops = {
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+#if defined(CORSTONE1000_FVP_MULTICORE)
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+ .pwr_domain_on = corstone1000_pwr_domain_on,
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+ .pwr_domain_on_finish = corstone1000_pwr_domain_on_finish,
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+ .validate_ns_entrypoint = corstone1000_validate_ns_entrypoint,
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+ .system_reset = corstone1000_system_reset,
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+#else
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+ .validate_ns_entrypoint = NULL,
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.system_reset = corstone1000_system_reset,
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- .validate_ns_entrypoint = NULL
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+#endif
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};
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
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index 35bb6ad5c..56e124f96 100644
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--- a/plat/arm/board/corstone1000/common/include/platform_def.h
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+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
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@@ -251,7 +251,20 @@
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*/
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#define ARM_LOCAL_STATE_OFF U(2)
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-#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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+#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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+
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+#if defined(CORSTONE1000_FVP_MULTICORE)
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+/* The secondary core entrypoint address points to bl31_warm_entrypoint
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+ * and the address size is 8 bytes */
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+#define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8)
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+
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+#define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \
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+ CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE)
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+#define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0)
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+#define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1)
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+#define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3)
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+#endif
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+
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE)
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diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
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index dcd0df844..71b7f324c 100644
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--- a/plat/arm/board/corstone1000/platform.mk
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+++ b/plat/arm/board/corstone1000/platform.mk
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@@ -31,6 +31,14 @@ override NEED_BL31 := yes
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NEED_BL32 := yes
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override NEED_BL33 := yes
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+ENABLE_MULTICORE := 0
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+ifneq ($(filter ${TARGET_PLATFORM}, fvp),)
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+ifeq (${ENABLE_MULTICORE},1)
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+$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE))
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+endif
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+endif
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+
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+
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# Include GICv2 driver files
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include drivers/arm/gic/v2/gicv2.mk
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--
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2.34.1
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‎meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc‎

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@@ -9,6 +9,7 @@ SRC_URI:append = " \
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file://0003-fix-spmd-remove-EL3-interrupt-registration.patch \
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file://0004-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \
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file://0005-fix-corstone1000-clean-the-cache-and-disable-interru.patch \
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file://0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \
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"
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TFA_DEBUG = "1"

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