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About the ADPCM's active5 signal. #73

@kunichiko

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@kunichiko

I have a question about the HDL code on this line.

wire active5 = (en_ch[1] && cur_ch[4]) || (en_ch[2] && cur_ch[5]) || (en_ch[2] && cur_ch[0]) || (en_ch[3] && cur_ch[1]) || (en_ch[4] && cur_ch[2]) || (en_ch[5] && cur_ch[3]);//{ cur_ch[3:0], cur_ch[5:4] } == en_ch;

This combinational logic looks asymmetric. Because..

(en_ch[1] && cur_ch[4])   ← diff = 3
(en_ch[2] && cur_ch[5])  ← diff = 3
(en_ch[2] && cur_ch[0])  ← diff = 4
(en_ch[3] && cur_ch[1])  ← diff = 4
(en_ch[4] && cur_ch[2])  ← diff = 4
(en_ch[5] && cur_ch[3])  ← diff = 4

Of course, I haven't fully understood the pipeline logic, but I believe this logic is incorrect.

Could you please inform me if there are any reasons why it is asymmetric?

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