modules.ini

[DEFAULT]
branch = master

# Verilog for various CPU cores
# -------------------------------------
#[blackparrot]
#type=cpu
#human_name = BlackParrot
#src = https://github.com/black-parrot/black-parrot.git
#contents = system_verilog
#license = License :: OSI Approved :: BSD License
#license_spdx = BSD-3-Clause
#git_hash = 7eb1037637d8515a259e204117b7b1273b1c2941

[lm32]
type = cpu
human_name = LatticeMico32
src = https://github.com/m-labs/lm32.git
contents = verilog
license = License :: OSI Approved :: Eclipse Public License 1.0 (EPL-1.0)
license_spdx = EPL-1.0

[minerva]
type = cpu
human_name = Minerva
src = https://github.com/lambdaconcept/minerva
contents = sources
license = License :: OSI Approved :: BSD License
license_spdx = BSD-2-Clause

[microwatt]
type = cpu
human_name = microwatt
src = https://github.com/antonblanchard/microwatt
contents = vhdl
#license = Open Hardware Description License Version 1.0
#license = License :: OSI Approved :: Creative Commons Attribution-ShareAlike 4.0 License (CC-BY-SA 4.0)
license = License :: OSI Approved
license_spdx = CC-BY-SA-4.0

[mor1kx]
type = cpu
human_name = OpenRISC1000
src = https://github.com/openrisc/mor1kx.git
contents = verilog
#license = Open Hardware Description License Version 1.0
license = License :: OSI Approved :: Mozilla Public License 2.0 (MPL 2.0)
license_spdx = MPL-2.0

[picorv32]
type = cpu
human_name = PicoRV32
src = https://github.com/cliffordwolf/picorv32
contents = verilog
license = License :: OSI Approved :: ISC License (ISCL)
license_spdx = ISC

[rocket]
type = cpu
human_name = Rocket
#src = https://github.com/litex-hub/litex-verilog-rocket
contents = verilog
license = License :: OSI Approved :: Apache Software License
license_spdx = Apache-2.0
# git tag v0.0 c06e2d16e4791bdd4bb36e661d36bec21c627c89
gen_src = https://github.com/chipsalliance/rocket-chip.git
git_describe = v0.0-7004-g1cf70ea2
git_hash = 1cf70ea2

[vexriscv]
type = cpu
human_name = VexRISCV
#src = https://github.com/litex-hub/litex-verilog-vexriscv
contents = verilog
license = License :: OSI Approved :: MIT License
license_spdx = MIT
gen_src = https://github.com/SpinalHDL/VexRISCV.git
git_describe = v1.0.1-265-g5f0c7a7
git_hash = 5f0c7a7faf6b65c907a93be6e3723e297d37ee71

[serv]
type = cpu
human_name = serv
src = https://github.com/olofk/serv
contents = verilog
license = License :: OSI Approved :: ISC License (ISCL)
license_spdx = ISC

[cv32e40p]
type = cpu
human_name = CV32E40P
src = https://github.com/antmicro/cv32e40p
contents = system_verilog
license = License :: OSI Approved :: Apache Software License
license_spdx = Apache-2.0

[ibex]
type = cpu
human_name = Ibex
src = https://github.com/lowRISC/ibex
contents = system_verilog
license = License :: OSI Approved :: Apache Software License
license_spdx = Apache-2.0

[opentitan]
type = misc
human_name = OpenTitan
src = https://github.com/lowRISC/opentitan
contents = resources
license = License :: OSI Approved :: Apache Software License
license_spdx = Apache-2.0

# Misc modules
# ------------------------------
#[compiler_rt]
#type = software
#human_name = LLVM Compiler RT Module
## src = https://github.com/llvm/llvm-project/tree/master/compiler-rt
#src = https://git.llvm.org/git/compiler-rt.git/
#contents = data
#license = License :: OSI Approved :: Apache Software License
#license_spdx = Apache-2.0
#branch = 81fb4f00c2cfe13814765968e09931ffa93b5138

[tapcfg]
type = misc
human_name = Ethernet TAP Config
src = https://github.com/enjoy-digital/tapcfg
contents = data
license = License :: OSI Approved :: GNU Lesser General Public License v2 (LGPLv2)
license_spdx = LGPL-2.1-only