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**Observation:* A new Vivado window will open specifically for editing this IP.
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2.**Modify Verilog Source:**
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In the *Sources* panel, you will see two files:
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*`axi_dyn_counter_v1_0.v`: The top-level wrapper (instantiates the AXI logic).
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*`axi_dyn_counter_v1_0_S00_AXI.v`: The actual AXI Lite implementation. **Edit this one.**
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***Why not the wrapper?**
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***The Wrapper (`_v1_0.v`):** This file is just the shell. Its job is to group multiple interfaces together. For example, if your IP had an AXI-Lite port *plus* an AXI-Stream video port *plus* an Interrupt line, the wrapper connects them all into one black box.
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***The Logic (`_S00_AXI.v`):** This file contains the **AXI Protocol Engine**. Vivado has pre-written the complex code that handles the valid/ready handshakes and address decoding. It gives you simple variables (`slv_reg0`) to work with. If you wrote code in the wrapper, you would have to write the AXI state machine yourself!
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***Open `axi_dyn_counter_v1_0_S00_AXI.v`.**
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***1. Add Logic (The Counter):**
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Scroll to the very bottom of the file (around line 400). You will see a placeholder:
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```verilog
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reg [31:0] internal_count;
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wire enable_signal;
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wire reset_signal;
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```
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// Add user logic here
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* **Map Registers:**
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```verilog
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slv_reg0: Control Register (Bit 0 \= Enable, Bit 1 \= Reset).
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slv_reg1: Output Register (The Count).
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// User logic ends
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```
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* **Implement Logic:** Add this block at the end of the file (before endmodule):
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```verilog
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// Mapping Control Bits
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Paste the following code *between* those lines:
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```verilog
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// -- Custom Signals --
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reg [31:0] internal_count;
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wire enable_signal;
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wire reset_signal;
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// -- Mappings --
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// slv_reg0[0] = Enable
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// slv_reg0[1] = Reset
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assign enable_signal = slv_reg0[0];
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assign reset_signal = slv_reg0[1];
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// Counter Logic
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// -- Counter Logic --
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always @( posedge S_AXI_ACLK ) begin
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if ( S_AXI_ARESETN == 1'b0 || reset_signal == 1'b1 ) begin
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internal_count <= 0;
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end else if ( enable_signal == 1'b1 ) begin
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internal_count <= internal_count + 1;
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end
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if ( S_AXI_ARESETN == 1'b0 || reset_signal == 1'b1 ) begin
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internal_count <= 0;
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end else if ( enable_signal == 1'b1 ) begin
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internal_count <= internal_count + 1;
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end
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end
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```
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```
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* **2. Map Output (The Read):**
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Scroll up slightly (around line 303). Find the long line that handles reading data (`assign S_AXI_RDATA = ...`).
*Effect:* When the processor reads Register 1 (Offset 0x4), it now sees our live `internal_count` instead of the static `slv_reg1` value.
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* **Hijack Read Logic:** Find the assign S\_AXI\_RDATA (or case statement) logic we touched in the Loopback project. Modify address h1 to read internal\_count instead of slv\_reg1.
* Click **Review and Package** \> **Re-Package IP**.
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* Close the temporary IP project.
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### **Part B: The Overlay Project**
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Now we build the system that PYNQ will load.
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> **Why a new project?**
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> * **Separation of Concerns:** `ip_counter_temp` is like a "Library Project" (specifically for creating the component). `pynq_overlay_demo` is the "Application Project" (where we wire components together).
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> * **Reusability:** By packaging the IP separately, you can now use `axi_dyn_counter` in *any* future Vivado project, just like you use the standard GPIO block.
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1. **Create Project:**
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* Create a new RTL Project: pynq\_overlay\_demo.
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* Create a new RTL Project: `pynq_overlay_demo`.
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* Board: **PYNQ-Z2**.
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2. **Setup Block Design:**
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2. **Add IP Repository:**
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(Crucial for finding your custom IP)
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* In the **Flow Navigator** (left), click **Settings**.
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* Go to **IP** > **Repository**.
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* Click **+** (Add Repository).
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* Navigate to your `ip_repo` folder (usually inside `ip_counter_temp/ip_repo`).
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* Select it and click **Select**. Click **OK**.
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3. **Setup Block Design:**
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* **Create Block Design** named design\_1.
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* **Add Zynq PS:** Add ZYNQ7 Processing System and run **Block Automation** (Apply Board Preset).
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* **Add GPIO:** Add AXI GPIO. Run **Connection Automation**.
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