We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent cad7d71 commit be32ab8Copy full SHA for be32ab8
Readme.md
@@ -11,7 +11,7 @@ NiceImage @todo --intro and doc =)
11
* [The python tools](/py_fpga/): to facilitate the acquisitions.
12
* [The cursed gateware](/verilog): for the current gateware linked to the python library.
13
14
-## Some Images
+## Some images, unipolar pulse at Vpulse = 5V
15
16
### Python setup
17
0 commit comments