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HDL parse is not good enough #18

@joezhouchenye

Description

@joezhouchenye

I have encountered three situations that symbolator generates an unexpected symbol.

  • Instantiation of a module whose name contains input, such as input_buffer. Symbolator will render this as a port "_buffer".
  • Comments in a Verilog module's parameter declaration part “#()”. Symbolator will also render this as an unexpected parameter port.
  • Special name in parameter. For example, a parameter named clock_ratio. Symbolator will add a triangle symbol for it.

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