Generating complete schematic out of VHDL files

[pidgeon777]

Hello, do you think one day symbolator could be used to parse one or more VHDL files to generate a schematic of the instanced components/wires?

[nobodywasishere]

You may be looking to use something like netlistsvg. I wrote a blog post on how to generate blog diagrams from VHDL using the open source FPGA toolchain here.

[mithro]

If you are using Sphinx, you might also want to consider https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/