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Simplify vMkRWire1, rename to __mkRWireSubmodule, expand the comment
This module only exists so that AAddSchedAssumps can create an AVInst for mkRWire of size 1. We could consider eliminating it by having BSC construct the AVInst in a better way. Until then, the interface is at least unneeded, so remove it -- eliminating the need for RWireN. Also remove vMkUnsafeRWire1, which is unneeded and should not have been created (when adding unsafe versions of the real modules).
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6 files changed

+15
-42
lines changed

6 files changed

+15
-42
lines changed

src/Libraries/Base1/Prelude.bs

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,6 @@ package Prelude(
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NumConArg(..), StarConArg(..), OtherConArg(..),
260260
MetaConsNamed(..), MetaConsAnon(..), MetaField(..),
261261

262-
primMethod, -- TODO: Needed only in PreludeBSV for vMkRWire1, should be removed.
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WrapField(..), WrapMethod(..), WrapPorts(..),
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Port(..), unPort, SplitPorts(..)
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) where

src/Libraries/Base1/PreludeBSV.bsv

Lines changed: 8 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -82,25 +82,16 @@ interface VRWire#(type a) ;
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method Bool whas() ;
8383
endinterface: VRWire
8484

85-
interface VRWireN#(numeric type n);
86-
method PrimAction wset(Bit#(n) datain);
87-
method Bit#(n) wget();
88-
method Bit#(1) whas();
89-
endinterface
90-
91-
// for addCFWire desugaring
92-
// This uses prim types like something coming from genwrap.
93-
module vMkRWire1(VRWireN#(1));
94-
85+
// __mkRWireSubmodule only exists so that BSC can get a handle on the
86+
// 'AVInst' for the submodule instantiation of 'vMkRWire', by applying
87+
// a few compiler stages to the definition. This occurs in
88+
// 'AAddSchedAssumps' where BSC implements the checking of
89+
// 'conflict_free' attributes by adding RWire writes to those rules,
90+
// and for that it needs to instantiate new RWire modules.
91+
//
92+
module __mkRWireSubmodule();
9593
(* hide *)
9694
VRWire#(Bit#(1)) _rw <- vMkRWire;
97-
function rw_wset(v);
98-
return toPrimAction(_rw.wset(v));
99-
endfunction
100-
method wset = primMethod(Cons("v", Nil), rw_wset);
101-
method wget = primMethod(Nil, _rw.wget);
102-
method whas = primMethod(Nil, pack(_rw.whas));
103-
10495
endmodule
10596

10697
interface VRWire0;
@@ -416,19 +407,6 @@ endmodule
416407

417408
// =======
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419-
// for addCFWire desugaring
420-
module vMkUnsafeRWire1(VRWireN#(1));
421-
422-
(* hide *)
423-
VRWire#(Bit#(1)) _rw <- vMkUnsafeRWire;
424-
method wset(v);
425-
return(toPrimAction(_rw.wset(v)));
426-
endmethod
427-
method wget = _rw.wget;
428-
method whas = pack(_rw.whas);
429-
430-
endmodule
431-
432410
import "BVI" RWire =
433411
module vMkUnsafeRWire (VRWire#(a))
434412
provisos (Bits#(a,sa));

src/comp/AAddSchedAssumps.hs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@ module AAddSchedAssumps(aAddSchedAssumps, aAddCFConditionWires) where
33
import CSyntax
44
import SymTab
55
import TypeCheck(topExpr)
6-
import CType
76
import Type
87
import qualified TIMonad as TIM(runTI)
98
import Flags(Flags, showElabProgress)
@@ -29,7 +28,6 @@ import PPrint
2928
import Pragma(ASchedulePragma)
3029
import Error(internalError, ErrMsg(..), showErrorList, ErrorHandle)
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import Id
32-
import Position(noPosition)
3331
import Util(unzipWith, ordPairBy)
3432
import Util(mapSnd)
3533

@@ -223,8 +221,8 @@ buildMethCondList uses = M.toList (M.fromListWith aOr uses')
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getRWireInstFn :: ErrorHandle -> Flags -> SymTab ->
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M.Map AId HExpr -> IO (Id -> AVInst)
225223
getRWireInstFn errh flags r alldefs = do
226-
let blobT = TAp tModule (TAp tVRWireN (cTNum 1 noPosition))
227-
case fst $ (TIM.runTI flags False r (topExpr blobT (CVar idVmkRWire1))) of
224+
let blobT = TAp tModule tEmpty
225+
case fst $ (TIM.runTI flags False r (topExpr blobT (CVar id__mkRWireSubmodule))) of
228226
Left errs -> internalError (ppReadable errs)
229227
Right (_,e') -> do
230228
let iexpr = iConvExpr errh flags r alldefs e'

src/comp/PreIds.hs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -510,9 +510,8 @@ idPrimAdd = prelude_id_no fsPrimAdd
510510
idPrimSub = prelude_id_no fsPrimSub
511511

512512
-- | Used by AddCFWire
513-
idVRWireN, idVmkRWire1, idWGet, idWSet, idWHas :: Id
514-
idVRWireN = prelude_bsv_id_no fsVRWireN
515-
idVmkRWire1 = prelude_bsv_id_no fsVmkRWire1
513+
id__mkRWireSubmodule, idWGet, idWSet, idWHas :: Id
514+
id__mkRWireSubmodule = prelude_bsv_id_no fs__mkRWireSubmodule
516515
idWGet = prelude_bsv_id_no fsWGet
517516
idWSet = prelude_bsv_id_no fsWSet
518517
idWHas = prelude_bsv_id_no fsWHas

src/comp/PreStrings.hs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -319,8 +319,7 @@ fsExposeCurrentReset = mkFString "exposeCurrentReset"
319319
fsNoClock = mkFString "noClock"
320320
fsNoReset = mkFString "noReset"
321321
fsPrimReplaceClockGate = mkFString "primReplaceClockGate"
322-
fsVRWireN = mkFString "VRWireN"
323-
fsVmkRWire1 = mkFString "vMkRWire1"
322+
fs__mkRWireSubmodule = mkFString "__mkRWireSubmodule"
324323
fsWGet = mkFString "wget"
325324
fsWSet = mkFString "wset"
326325
fsWHas = mkFString "whas"

src/comp/Type.hs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,10 +76,10 @@ tRules = TCon (TyCon idRules (Just KStar) TIabstract)
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tRulesAt :: Position -> Type
7777
tRulesAt pos = TCon (TyCon (idRulesAt pos) (Just KStar) TIabstract)
7878

79-
tSchedPragma, tModule, tVRWireN, tId, t32 :: Type
79+
tSchedPragma, tModule, tEmpty, tId, t32 :: Type
8080
tSchedPragma = TCon (TyCon idSchedPragma (Just KStar) TIabstract)
8181
tModule = TCon (TyCon idModule (Just (Kfun KStar KStar)) TIabstract)
82-
tVRWireN = TCon (TyCon idVRWireN (Just (Kfun KNum KStar)) (TIstruct SStruct [idWSet, idWGet, idWHas]))
82+
tEmpty = TCon (TyCon idEmpty (Just KStar) (TIstruct (SInterface []) []))
8383
tId = TCon (TyCon idId (Just (Kfun KStar KStar)) TIabstract)
8484
t32 = tOfSize 32 noPosition
8585

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