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1 parent d4cd1a7 commit 5fe0639Copy full SHA for 5fe0639
testsuite/bsc.verilog/noinline/noinline.exp
@@ -41,9 +41,6 @@ test_c_veri_bsv_modules \
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module_testLessPatternsBSVFunction \
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sysNoInline_LessPatternsThanArgs.out.expected
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-# The typedef fails because BSC doesn't expand the synonym before checking
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-# to see if the result type is in Bits, so the user gets a proviso error
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-# (bug 1466)
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compile_verilog_pass NoInline_LessPatternsThanArgs_BSV_TypeDef.bsv
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# -----
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