Skip to content

Commit 6f08aca

Browse files
authored
Merge pull request #275 from krcb197/268-further-optimise-the-property-tests
Optimise property and name map tests
2 parents d9759ee + 690c264 commit 6f08aca

2 files changed

Lines changed: 203 additions & 94 deletions

File tree

src/peakrdl_python/lib_test/_common_base_test_class.py

Lines changed: 154 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
from ..lib import MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy
4040
from ..lib import MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy
4141
from ..lib.base_register import BaseReg
42+
from ..lib import Node
4243
from ..lib import Base
4344
from .utilities import get_field_bitmask_int, get_field_inv_bitmask
4445
from ..sim_lib.simulator import BaseSimulator
@@ -122,7 +123,12 @@ def _single_field_property_test(self, *,
122123
low: int,
123124
high: int,
124125
is_volatile: bool,
125-
default: Optional[int]) -> None:
126+
default: Optional[int],
127+
rdl_name: Optional[str],
128+
rdl_desc: Optional[str],
129+
parent_full_inst_name: str,
130+
inst_name: str
131+
) -> None:
126132
self.assertEqual(fut.lsb, lsb)
127133
self.assertEqual(fut.msb, msb)
128134
self.assertEqual(fut.low, low)
@@ -156,17 +162,45 @@ def _single_field_property_test(self, *,
156162
else:
157163
self.assertEqual(fut.default, default)
158164

165+
self.__single_node_rdl_name_and_desc_test(dut=fut,
166+
rdl_name=rdl_name,
167+
rdl_desc=rdl_desc)
168+
169+
self.__test_node_inst_name(dut=fut,
170+
parent_full_inst_name=parent_full_inst_name,
171+
inst_name=inst_name)
172+
173+
self.__bad_attribute_test(dut=fut)
174+
175+
# pylint:disable-next=too-many-arguments
159176
def _single_register_property_test(self, *,
160177
rut: BaseReg,
161178
address: int,
162179
width: int,
163-
accesswidth: Optional[int]) -> None:
180+
accesswidth: Optional[int],
181+
size: int,
182+
rdl_name: Optional[str],
183+
rdl_desc: Optional[str],
184+
parent_full_inst_name: str,
185+
inst_name: str
186+
) -> None:
164187
self.assertEqual(rut.address, address)
165188
self.assertEqual(rut.width, width)
166189
if accesswidth is not None:
167190
self.assertEqual(rut.accesswidth, accesswidth)
168191
else:
169192
self.assertEqual(rut.accesswidth, width)
193+
self.assertEqual(rut.size, size)
194+
195+
self.__single_node_rdl_name_and_desc_test(dut=rut,
196+
rdl_name=rdl_name,
197+
rdl_desc=rdl_desc)
198+
199+
self.__test_node_inst_name(dut=rut,
200+
parent_full_inst_name=parent_full_inst_name,
201+
inst_name=inst_name)
202+
203+
self.__bad_attribute_test(dut=rut)
170204

171205
# pylint:disable-next=too-many-arguments
172206
def _single_memory_property_test(self, *,
@@ -175,7 +209,13 @@ def _single_memory_property_test(self, *,
175209
width: int,
176210
entries: int,
177211
accesswidth: Optional[int],
178-
array_typecode: Optional[str]) -> None:
212+
array_typecode: Optional[str],
213+
size: int,
214+
rdl_name: Optional[str],
215+
rdl_desc: Optional[str],
216+
parent_full_inst_name: str,
217+
inst_name: str
218+
) -> None:
179219
self.assertEqual(mut.address, address)
180220
self.assertEqual(mut.width, width)
181221
self.assertEqual(mut.entries, entries)
@@ -187,8 +227,63 @@ def _single_memory_property_test(self, *,
187227
self.assertEqual(mut.array_typecode, array_typecode)
188228
else:
189229
self.assertIsNone(array_typecode)
230+
self.assertEqual(mut.size, size)
231+
232+
self.__single_node_rdl_name_and_desc_test(dut=mut,
233+
rdl_name=rdl_name,
234+
rdl_desc=rdl_desc)
235+
236+
self.__test_node_inst_name(dut=mut,
237+
parent_full_inst_name=parent_full_inst_name,
238+
inst_name=inst_name)
239+
240+
self.__bad_attribute_test(dut=mut)
241+
242+
# pylint:disable-next=too-many-arguments
243+
def _single_addrmap_property_test(self, *,
244+
dut: Union[AddressMap, AsyncAddressMap],
245+
size: int,
246+
rdl_name: Optional[str],
247+
rdl_desc: Optional[str],
248+
parent_full_inst_name: Optional[str],
249+
inst_name: str
250+
) -> None:
251+
252+
self.assertEqual(dut.size, size)
253+
254+
self.__single_node_rdl_name_and_desc_test(dut=dut,
255+
rdl_name=rdl_name,
256+
rdl_desc=rdl_desc)
257+
258+
self.__test_node_inst_name(dut=dut,
259+
parent_full_inst_name=parent_full_inst_name,
260+
inst_name=inst_name)
261+
262+
self.__bad_attribute_test(dut=dut)
263+
264+
# pylint:disable-next=too-many-arguments
265+
def _single_regfile_property_test(self, *,
266+
dut: Union[RegFile, AsyncRegFile],
267+
size: int,
268+
rdl_name: Optional[str],
269+
rdl_desc: Optional[str],
270+
parent_full_inst_name: str,
271+
inst_name: str
272+
) -> None:
273+
274+
self.assertEqual(dut.size, size)
275+
276+
self.__single_node_rdl_name_and_desc_test(dut=dut,
277+
rdl_name=rdl_name,
278+
rdl_desc=rdl_desc)
190279

191-
def _single_node_rdl_name_and_desc_test(self,
280+
self.__test_node_inst_name(dut=dut,
281+
parent_full_inst_name=parent_full_inst_name,
282+
inst_name=inst_name)
283+
284+
self.__bad_attribute_test(dut=dut)
285+
286+
def __single_node_rdl_name_and_desc_test(self,
192287
dut: Base,
193288
rdl_name: Optional[str],
194289
rdl_desc: Optional[str]) -> None:
@@ -205,16 +300,40 @@ def _single_node_rdl_name_and_desc_test(self,
205300
else:
206301
self.assertEqual(dut.rdl_desc, rdl_desc)
207302

208-
def _test_node_inst_name(self,
209-
dut: Base,
210-
parent_full_inst_name:str,
211-
inst_name:str) -> None:
303+
def __test_node_inst_name(self,
304+
dut: Base,
305+
parent_full_inst_name:Optional[str],
306+
inst_name:str) -> None:
212307
"""
213308
Test the `inst_name` and `full_inst_name` attributes of a node
214309
"""
215310
self.assertEqual(dut.inst_name, inst_name)
216-
full_inst_name = parent_full_inst_name + '.' + inst_name
217-
self.assertEqual(dut.full_inst_name, full_inst_name)
311+
if parent_full_inst_name is None:
312+
# root node (which has no parent)
313+
self.assertEqual(dut.full_inst_name, inst_name)
314+
else:
315+
full_inst_name = parent_full_inst_name + '.' + inst_name
316+
self.assertEqual(dut.full_inst_name, full_inst_name)
317+
318+
def __bad_attribute_test(self, dut: Base) -> None:
319+
"""
320+
Check that adding an attribute fails, the __slots__ should prevent this
321+
322+
The attribute name: cppkbrgmgeloagvfgjjeiiushygirh was randomly generated to be unlikely to
323+
every be a attribute name
324+
"""
325+
with self.assertRaises(AttributeError):
326+
dut.cppkbrgmgeloagvfgjjeiiushygirh = 1 # type: ignore[attr-defined,union-attr]
327+
328+
def __test_name_map(self, dut: Node, child_names: set[str]) -> None:
329+
"""
330+
Test that the get_child_by_system_rdl_name and systemrdl_python_child_name_map are
331+
populated correctly
332+
"""
333+
self.assertCountEqual(dut.systemrdl_python_child_name_map, child_names)
334+
self.assertEqual(set(dut.systemrdl_python_child_name_map.keys()), child_names)
335+
for child_name in child_names:
336+
self.assertEqual(dut.get_child_by_system_rdl_name(child_name).inst_name, child_name)
218337

219338
def _test_field_iterators(self, *,
220339
rut: Union[RegReadOnly,
@@ -262,6 +381,9 @@ def _test_field_iterators(self, *,
262381
child_field_names = {field.inst_name for field in rut.fields}
263382
self.assertEqual(readable_fields | writeable_fields, child_field_names)
264383

384+
# Check the child name map
385+
self.__test_name_map(dut=rut, child_names= readable_fields | writeable_fields)
386+
265387
def _test_register_iterators(self,
266388
dut: Union[AddressMap, AsyncAddressMap, RegFile, AsyncRegFile,
267389
MemoryReadOnly, MemoryReadOnlyLegacy,
@@ -308,6 +430,19 @@ def _test_register_iterators(self,
308430
self.assertEqual(readable_registers.rolled | writeable_registers.rolled,
309431
child_reg_names)
310432

433+
# The register file and addrmap have other items in their child map so it has to be
434+
# tested at the next level up, however, a memory only has child registers
435+
if isinstance(dut, (MemoryReadOnly, MemoryReadOnlyLegacy,
436+
MemoryWriteOnly, MemoryWriteOnlyLegacy,
437+
MemoryReadWrite, MemoryReadWriteLegacy,
438+
MemoryAsyncReadOnly, MemoryAsyncReadOnlyLegacy,
439+
MemoryAsyncWriteOnly, MemoryAsyncWriteOnlyLegacy,
440+
MemoryAsyncReadWrite, MemoryAsyncReadWriteLegacy)):
441+
# Check the child name map
442+
self.__test_name_map(dut=dut,
443+
child_names=readable_registers.rolled |
444+
writeable_registers.rolled)
445+
311446

312447
def _test_memory_iterators(self,
313448
dut: Union[AddressMap, AsyncAddressMap],
@@ -339,6 +474,10 @@ def _test_addrmap_iterators(self, *,
339474
self.__test_section_iterators(dut=dut,
340475
sections=sections)
341476

477+
# Check the child name map
478+
self.__test_name_map(dut=dut, child_names=memories.rolled | readable_registers.rolled |
479+
writeable_registers.rolled | sections.rolled)
480+
342481
def _test_regfile_iterators(self,
343482
dut: Union[RegFile, AsyncRegFile],
344483
sections: NodeIterators,
@@ -350,3 +489,8 @@ def _test_regfile_iterators(self,
350489
self.__test_section_iterators(dut=dut,
351490
sections=sections)
352491
self.assertFalse(hasattr(dut, 'get_memories'))
492+
493+
# Check the child name map
494+
self.__test_name_map(dut=dut, child_names=readable_registers.rolled |
495+
writeable_registers.rolled |
496+
sections.rolled)

0 commit comments

Comments
 (0)