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Merge pull request #166 from apstrike/main
Incorrect top level name when parameter is set at command line
2 parents e4b2521 + f3808a1 commit 8f9211d

8 files changed

Lines changed: 51 additions & 27 deletions

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‎.github/workflows/action.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,7 @@ jobs:
175175
peakrdl python tests/testcases/extended_memories.rdl -o peakrdl_out/raw/
176176
peakrdl python tests/testcases/user_defined_properties.rdl -o peakrdl_out/raw/ --udp bool_property_to_include
177177
peakrdl python tests/testcases/reserved_elements.rdl -o peakrdl_out/raw/ --hide_regex "(?:[\w_\[\]]+\.)+RSVD"
178+
peakrdl python tests/testcases/parametrised_top.rdl -o peakrdl_out/raw/ -P MY_PARAM=3
178179
python -m unittest discover -s peakrdl_out/raw
179180
180181
peakrdl python tests/testcases/basic.rdl -o peakrdl_out/raw_async/ --async

‎src/peakrdl_python/__about__.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,4 +17,4 @@
1717
1818
Variables that describes the peakrdl-python Package
1919
"""
20-
__version__ = "1.0.1"
20+
__version__ = "1.1.0"

‎src/peakrdl_python/exporter.py‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -735,8 +735,18 @@ def _build_node_type_table(self, node: AddressableNode,
735735
# de-duplicate the values
736736
raise RuntimeError("node is already in the lookup dictionary")
737737

738-
cand_type_name = get_fully_qualified_type_name(child_node)
738+
if child_node == node:
739+
# in the case of the top node the type name should match the instance name
740+
cand_type_name = child_node.inst_name
741+
else:
742+
cand_type_name = get_fully_qualified_type_name(child_node)
739743
if cand_type_name in self.node_type_name.values():
744+
if child_node == node:
745+
raise RuntimeError(
746+
f'Top Node name {cand_type_name} already used by instance ' \
747+
+ str(list(self.node_type_name.keys())
748+
[list(self.node_type_name.values()).index(cand_type_name)])
749+
)
740750
self.node_type_name[child_inst] = cand_type_name + '_0x' + hex(hash(child_inst))
741751
else:
742752
self.node_type_name[child_inst] = cand_type_name

‎src/peakrdl_python/templates/addrmap_simulation_tb.py.jinja‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,10 @@ from enum import IntEnum
3535
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}sim_lib.register import Register,MemoryRegister
3636
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}sim_lib.field import Field
3737

38-
from ._{{top_node.inst_name}}_sim_test_base import {{top_node.type_name}}_SimTestCase, {{top_node.type_name}}_SimTestCase_BlockAccess
38+
from ._{{top_node.inst_name}}_sim_test_base import {{top_node.inst_name}}_SimTestCase, {{top_node.inst_name}}_SimTestCase_BlockAccess
3939
from ._{{top_node.inst_name}}_sim_test_base import __name__ as base_name
4040

41-
class {{fq_block_name}}_single_access({{top_node.type_name}}_SimTestCase): # type: ignore[valid-type,misc]
41+
class {{fq_block_name}}_single_access({{top_node.inst_name}}_SimTestCase): # type: ignore[valid-type,misc]
4242

4343
{% if asyncoutput %}async {% endif %}def test_register_read_and_write(self) -> None:
4444
"""
@@ -335,7 +335,7 @@ class {{fq_block_name}}_single_access({{top_node.type_name}}_SimTestCase): # typ
335335

336336

337337

338-
class {{fq_block_name}}_block_access({{top_node.type_name}}_SimTestCase_BlockAccess): # type: ignore[valid-type,misc]
338+
class {{fq_block_name}}_block_access({{top_node.inst_name}}_SimTestCase_BlockAccess): # type: ignore[valid-type,misc]
339339
"""
340340
tests for all the block access methods
341341
"""

‎src/peakrdl_python/templates/addrmap_tb.py.jinja‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -35,9 +35,9 @@ from enum import IntEnum
3535

3636
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import RegisterWriteVerifyError, UnsupportedWidthError
3737

38-
from ..reg_model.{{top_node.type_name}} import {{top_node.type_name}}_cls
38+
from ..reg_model.{{top_node.inst_name}} import {{top_node.inst_name}}_cls
3939
{% for property_enum in dependent_property_enum %}
40-
from ..reg_model.{{top_node.type_name}} import {{property_enum.type_name}}_property_enumcls
40+
from ..reg_model.{{top_node.inst_name}} import {{property_enum.type_name}}_property_enumcls
4141
{% endfor %}
4242

4343

@@ -67,12 +67,12 @@ from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import
6767
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import Field
6868
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import Reg
6969

70-
from ._{{top_node.inst_name}}_test_base import {{top_node.type_name}}_TestCase, {{top_node.type_name}}_TestCase_BlockAccess, {{top_node.type_name}}_TestCase_AltBlockAccess
70+
from ._{{top_node.inst_name}}_test_base import {{top_node.inst_name}}_TestCase, {{top_node.inst_name}}_TestCase_BlockAccess, {{top_node.inst_name}}_TestCase_AltBlockAccess
7171
from ._{{top_node.inst_name}}_test_base import __name__ as base_name
7272

7373
{% from 'addrmap_udp_property.py.jinja' import udp_property_dict_entry with context %}
7474

75-
class {{fq_block_name}}_single_access({{top_node.type_name}}_TestCase): # type: ignore[valid-type,misc]
75+
class {{fq_block_name}}_single_access({{top_node.inst_name}}_TestCase): # type: ignore[valid-type,misc]
7676

7777
def test_inst_name(self) -> None:
7878
"""
@@ -1329,7 +1329,7 @@ class {{fq_block_name}}_single_access({{top_node.type_name}}_TestCase): # type:
13291329

13301330

13311331

1332-
class {{fq_block_name}}_block_access({{top_node.type_name}}_TestCase_BlockAccess): # type: ignore[valid-type,misc]
1332+
class {{fq_block_name}}_block_access({{top_node.inst_name}}_TestCase_BlockAccess): # type: ignore[valid-type,misc]
13331333
"""
13341334
tests for all the block access methods
13351335
"""
@@ -1488,7 +1488,7 @@ class {{fq_block_name}}_block_access({{top_node.type_name}}_TestCase_BlockAccess
14881488

14891489
{%- endfor %}
14901490

1491-
class {{fq_block_name}}_alt_block_access({{top_node.type_name}}_TestCase_AltBlockAccess): # type: ignore[valid-type,misc]
1491+
class {{fq_block_name}}_alt_block_access({{top_node.inst_name}}_TestCase_AltBlockAccess): # type: ignore[valid-type,misc]
14921492
"""
14931493
tests for all the block access methods with the alternative callbacks, this is a simpler
14941494
version of the tests above

‎src/peakrdl_python/templates/baseclass_simulation_tb.py.jinja‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -37,23 +37,23 @@ from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import
3737
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import NormalCallbackSet{% if legacy_block_access %}Legacy{% endif %}
3838
{% endif %}
3939

40-
from ._{{top_node.inst_name}}_test_base import {{top_node.type_name}}_TestCase, {{top_node.type_name}}_TestCase_BlockAccess
40+
from ._{{top_node.inst_name}}_test_base import {{top_node.inst_name}}_TestCase, {{top_node.inst_name}}_TestCase_BlockAccess
4141

42-
from ..reg_model.{{top_node.type_name}} import {{top_node.type_name}}_cls
43-
from ..sim.{{top_node.type_name}} import {{top_node.type_name}}_simulator_cls
42+
from ..reg_model.{{top_node.inst_name}} import {{top_node.inst_name}}_cls
43+
from ..sim.{{top_node.inst_name}} import {{top_node.inst_name}}_simulator_cls
4444

45-
class {{top_node.type_name}}_SimTestCase({{top_node.type_name}}_TestCase): # type: ignore[valid-type,misc]
45+
class {{top_node.inst_name}}_SimTestCase({{top_node.inst_name}}_TestCase): # type: ignore[valid-type,misc]
4646

4747
def setUp(self) -> None:
48-
self.sim = {{top_node.type_name}}_simulator_cls(address=0)
49-
self.dut = {{top_node.type_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=self.sim.read,
48+
self.sim = {{top_node.inst_name}}_simulator_cls(address=0)
49+
self.dut = {{top_node.inst_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=self.sim.read,
5050
write_callback=self.sim.write))
5151

52-
class {{top_node.type_name}}_SimTestCase_BlockAccess({{top_node.type_name}}_TestCase_BlockAccess): # type: ignore[valid-type,misc]
52+
class {{top_node.inst_name}}_SimTestCase_BlockAccess({{top_node.inst_name}}_TestCase_BlockAccess): # type: ignore[valid-type,misc]
5353

5454
def setUp(self) -> None:
55-
self.sim = {{top_node.type_name}}_simulator_cls(address=0)
56-
self.dut = {{top_node.type_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=self.sim.read,
55+
self.sim = {{top_node.inst_name}}_simulator_cls(address=0)
56+
self.dut = {{top_node.inst_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=self.sim.read,
5757
write_callback=self.sim.write,
5858
read_block_callback=self.sim.read_block,
5959
write_block_callback=self.sim.write_block))

‎src/peakrdl_python/templates/baseclass_tb.py.jinja‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}lib import
3838
{% endif %}
3939

4040

41-
from ..reg_model.{{top_node.type_name}} import {{top_node.type_name}}_cls
41+
from ..reg_model.{{top_node.inst_name}} import {{top_node.inst_name}}_cls
4242
{% if asyncoutput %}
4343
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}sim_lib.dummy_callbacks import async_dummy_read as read_addr_space
4444
from {% if skip_lib_copy %}src.peakrdl_python.{% else %}..{% endif %}sim_lib.dummy_callbacks import async_dummy_write as write_addr_space
@@ -83,10 +83,10 @@ else:
8383
TestCaseBase = unittest.TestCase
8484
{% endif %}
8585

86-
class {{top_node.type_name}}_TestCase(TestCaseBase): # type: ignore[valid-type,misc]
86+
class {{top_node.inst_name}}_TestCase(TestCaseBase): # type: ignore[valid-type,misc]
8787

8888
def setUp(self) -> None:
89-
self.dut = {{top_node.type_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=read_callback,
89+
self.dut = {{top_node.inst_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=read_callback,
9090
write_callback=write_callback))
9191

9292
@staticmethod
@@ -106,22 +106,22 @@ class {{top_node.type_name}}_TestCase(TestCaseBase): # type: ignore[valid-type,m
106106
result |= 1 << (number_bits - 1 - i)
107107
return result
108108

109-
class {{top_node.type_name}}_TestCase_BlockAccess(TestCaseBase): # type: ignore[valid-type,misc]
109+
class {{top_node.inst_name}}_TestCase_BlockAccess(TestCaseBase): # type: ignore[valid-type,misc]
110110

111111
def setUp(self) -> None:
112-
self.dut = {{top_node.type_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=read_callback,
112+
self.dut = {{top_node.inst_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if legacy_block_access %}Legacy{% endif %}(read_callback=read_callback,
113113
write_callback=write_callback,
114114
read_block_callback=read_block_callback,
115115
write_block_callback=write_block_callback))
116116

117-
class {{top_node.type_name}}_TestCase_AltBlockAccess(TestCaseBase): # type: ignore[valid-type,misc]
117+
class {{top_node.inst_name}}_TestCase_AltBlockAccess(TestCaseBase): # type: ignore[valid-type,misc]
118118
"""
119119
Based test to use with the alternative call backs, this allow the legacy output API to be tested
120120
with the new callbacks and visa versa.
121121
"""
122122

123123
def setUp(self) -> None:
124-
self.dut = {{top_node.type_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if not legacy_block_access %}Legacy{% endif %}(
124+
self.dut = {{top_node.inst_name}}_cls(callbacks={% if asyncoutput %}AsyncCallbackSet{% else %}NormalCallbackSet{% endif %}{% if not legacy_block_access %}Legacy{% endif %}(
125125
read_callback=read_callback,
126126
write_callback=write_callback,
127127
read_block_callback=read_block_callback_alt,

‎tests/testcases/parametrised_top.rdl‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
addrmap parametrised_top #(bit MY_PARAM = 12) {
2+
3+
default regwidth = 32;
4+
default accesswidth = 32;
5+
6+
reg {
7+
default sw = rw;
8+
default hw = rw;
9+
name = "ReadWriteRegister";
10+
field {} my_field[32] = 0;
11+
} my_reg[MY_PARAM];
12+
13+
};

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