Merge pull request #203 from krcb197/202-shared-address-registers-do-not-get-simulated-correctly

shared address registers do not get simulated correctly

Author: krcb197

src/peakrdl_python/__about__.py

@@ -17,4 +17,4 @@
 
 Variables that describes the peakrdl-python Package
 """
-__version__ = "1.2.1rc4"
+__version__ = "1.3.0"

src/peakrdl_python/exporter.py

@@ -382,15 +382,39 @@ def __export_simulator(self, *,
                            asyncoutput: bool,
                            legacy_block_access: bool) -> None:
 
+        # as a result of issue 202, where two registers existed at that same address,
+        # rather than iterating through the registers within the Jinja template
+        # we iterate through them in in advance so that cases of two registers at that same
+        # address can be identified
+        reg_dict:dict[int, Union[list[RegNode],RegNode]] = {}
+        for node in filter(lambda x : isinstance(x, RegNode),  top_block.descendants(unroll=True)):
+            if not isinstance(node, RegNode):
+                raise TypeError(f'node should be a register, got {type(node)}')
+            reg_addr = node.absolute_address
+            if reg_addr in reg_dict:
+                existing_entry = reg_dict[reg_addr]
+                # if the entry is already list simply append to it
+                if isinstance(existing_entry, list):
+                    existing_entry.append(node)
+                elif isinstance(existing_entry, RegNode):
+                    reg_dict[reg_addr] = [existing_entry, node]
+                else:
+                    raise TypeError(f'exiting entry of unexpected type: {type(existing_entry)}')
+            else:
+                reg_dict[reg_addr] = node
+
+
         context = {
             'top_node': top_block,
+            'reg_dict': reg_dict,
             'systemrdlRegNode': RegNode,
             'systemrdlMemNode': MemNode,
             'isinstance': isinstance,
             'asyncoutput': asyncoutput,
             'skip_lib_copy': skip_lib_copy,
             'version': __version__,
             'legacy_block_access': legacy_block_access,
+            'list': list
         }
 
         context.update(self.user_template_context)

src/peakrdl_python/sim_lib/simulator.py

@@ -81,10 +81,11 @@ def __init__(self, address: int):
         self.address = address
 
     @abstractmethod
-    def _build_registers(self) -> dict[int, Union[MemoryRegister, Register]]:
+    def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Register]],
+                                                  Union[MemoryRegister, Register]]]:
         """
-        populate the register structure, this method is intended to written by the generated code
-        based on then design
+        populate the register structure, this method is intended to implemented by the generated
+        code based on then design
         """
 
     @abstractmethod
@@ -145,7 +146,15 @@ def _read(self, addr: int,
         # see if the address is a register first this ensures that registers in memories are
         # accessed directly
         if addr in self._registers:
-            return self._registers[addr].read()
+            addr_entry = self._registers[addr]
+            if isinstance(addr_entry, list):
+                # search the list for a readable register
+                for inner_reg in addr_entry:
+                    # pylint: disable-next=protected-access
+                    if inner_reg._readable:
+                        return inner_reg.read()
+            else:
+                return addr_entry.read()
 
         potential_memory = self.memory_for_address(address=addr)
         if potential_memory is not None:
@@ -164,7 +173,14 @@ def _write(self, addr: int,
         # see if the address is a register first this ensures that registers in memories are
         # accessed directly
         if addr in self._registers:
-            self._registers[addr].write(data)
+            addr_entry = self._registers[addr]
+            if isinstance(addr_entry, list):
+                for inner_reg in addr_entry:
+                    # pylint: disable-next=protected-access
+                    if inner_reg._writable:
+                        inner_reg.write(data)
+            else:
+                addr_entry.write(data)
         else:
             potential_memory = self.memory_for_address(address=addr)
             if potential_memory is not None:
@@ -244,8 +260,13 @@ def register_by_full_name(self, name: str) -> Union[MemoryRegister, Register]:
 
         """
         for reg in self._registers.values():
-            if reg.full_inst_name == name:
-                return reg
+            if isinstance(reg, list):
+                for reg_list_entry in reg:
+                    if reg_list_entry.full_inst_name == name:
+                        return reg_list_entry
+            else:
+                if reg.full_inst_name == name:
+                    return reg
 
         raise ValueError(f'register name not matched: {name}')
 
@@ -260,9 +281,15 @@ def field_by_full_name(self, name: str) -> Field:
 
         """
         for reg in self._registers.values():
-            for field in reg.fields:
-                if field.full_inst_name == name:
-                    return field
+            if isinstance(reg, list):
+                for reg_list_entry in reg:
+                    for field in reg_list_entry.fields:
+                        if field.full_inst_name == name:
+                            return field
+            else:
+                for field in reg.fields:
+                    if field.full_inst_name == name:
+                        return field
 
         raise ValueError(f'field name not matched: {name}')
 
@@ -282,12 +309,21 @@ def node_by_full_name(self, name: str) -> Union[Memory, MemoryRegister, Register
                 return mem.memory
 
         for reg in self._registers.values():
-            if reg.full_inst_name == name:
-                return reg
-
-            for field in reg.fields:
-                if field.full_inst_name == name:
-                    return field
+            if isinstance(reg, list):
+                for reg_list_entry in reg:
+                    if reg_list_entry.full_inst_name == name:
+                        return reg_list_entry
+
+                    for field in reg_list_entry.fields:
+                        if field.full_inst_name == name:
+                            return field
+            else:
+                if reg.full_inst_name == name:
+                    return reg
+
+                for field in reg.fields:
+                    if field.full_inst_name == name:
+                        return field
 
         raise ValueError(f'node name not matched: {name}')
 

src/peakrdl_python/templates/sim_addrmap.py.jinja

@@ -30,18 +30,24 @@ from {% if skip_lib_copy %}peakrdl_python.{% else %}..{% endif %}sim_lib.simulat
 from {% if skip_lib_copy %}peakrdl_python.{% else %}..{% endif %}sim_lib.simulator import Simulator{% if legacy_block_access %}Legacy{% endif %}
 {%- endif %}
 
-class {{top_node.inst_name}}_simulator_cls(Simulator{% if legacy_block_access %}Legacy{% endif %}):
-
-    def _build_registers(self) -> dict[int, Union[MemoryRegister, Register]]:
-        return {
-        {%- for node in top_node.descendants(unroll=True) -%}
-            {% if isinstance(node, systemrdlRegNode) %}
-            {{node.absolute_address}} : {% if isinstance(node.parent, systemrdlMemNode) %}MemoryRegister(memory=self.memory_for_address_with_exception({{node.absolute_address}}).memory,memory_address_offset={{node.address_offset}},{% else %}Register({% endif %}width={{node.size*8}}, full_inst_name='{{'.'.join(node.get_path_segments())}}', readable={{node.has_sw_readable}}, writable={{node.has_sw_writable}},
+{%- macro single_reg_entry(node) %}
+    {% if isinstance(node.parent, systemrdlMemNode) %}MemoryRegister(memory=self.memory_for_address_with_exception({{node.absolute_address}}).memory,memory_address_offset={{node.address_offset}},{% else %}Register({% endif %}width={{node.size*8}}, full_inst_name='{{'.'.join(node.get_path_segments())}}', readable={{node.has_sw_readable}}, writable={{node.has_sw_writable}},
                                          fields=[
                                                 {%- for field in node.fields() -%}
                                                 FieldDefinition(high={{field.high}}, low={{field.low}}, msb={{field.msb}}, lsb={{field.lsb}}, inst_name='{{field.inst_name}}'),
                                                 {%- endfor %}
-                                                ]),
+                                                ])
+{%- endmacro %}
+
+class {{top_node.inst_name}}_simulator_cls(Simulator{% if legacy_block_access %}Legacy{% endif %}):
+
+    def _build_registers(self) -> dict[int, Union[list[Union[MemoryRegister, Register]], Union[MemoryRegister, Register]]]:
+        return {
+        {%- for addr, addr_entry in reg_dict.items() -%}
+            {% if isinstance(addr_entry, list) %}
+            {{addr}} : [{% for node in addr_entry %}{{single_reg_entry(node)}},{% endfor %}],
+            {% else %}
+            {{addr}} : {{single_reg_entry(addr_entry)}},
             {%- endif %}
         {%- endfor %}
         }

tests/testcases/shared_register_issue_202

@@ -0,0 +1,24 @@
+addrmap shared_register_issue_202 {
+
+     reg {
+        field { fieldwidth=1; sw=rw; } enable;
+     } control ;
+
+     reg {
+        field { fieldwidth=16; sw=w; hw=r; } data;
+     } tx @ 4;
+
+     reg {
+        field { fieldwidth=16; sw=r; hw=w; } data;
+     } rx @ 4;
+
+     reg {
+        field { fieldwidth=8; sw=r; hw=w; } count;
+     } rx_fifo_fill;
+
+     reg {
+        field { fieldwidth=8; sw=r; hw=w; } count;
+     } tx_fifo_fill;
+
+};
+