Merge pull request #82 from krcb197/81-templates-error-on-systemrdl-signalnodes

81 templates error on systemrdl signalnodes

Author: krcb197

src/peakrdl_python/__about__.py

@@ -1,4 +1,4 @@
 """
 Variables that describes the PeakRDL Python Package
 """
-__version__ = "0.3.10"
+__version__ = "0.3.11"

src/peakrdl_python/exporter.py

@@ -12,6 +12,7 @@
 
 from systemrdl.node import RootNode, Node, RegNode, AddrmapNode, RegfileNode # type: ignore
 from systemrdl.node import FieldNode, MemNode, AddressableNode # type: ignore
+from systemrdl.node import SignalNode # type: ignore
 from systemrdl.rdltypes import OnReadType, OnWriteType, PropertyReference # type: ignore
 
 from .systemrdl_node_utility_functions import get_reg_readable_fields, get_reg_writable_fields, \
@@ -131,6 +132,7 @@ def export(self, node: Node, path: str,
                 'systemrdlAddrmapNode': AddrmapNode,
                 'systemrdlMemNode': MemNode,
                 'systemrdlAddressableNode': AddressableNode,
+                'systemrdlSignalNode': SignalNode,
                 'OnWriteType': OnWriteType,
                 'OnReadType': OnReadType,
                 'PropertyReference': PropertyReference,

src/peakrdl_python/templates/addrmap.py.jinja

@@ -243,6 +243,8 @@ class {{get_fully_qualified_type_name(node)}}_cls(AddressMap):
             '{{child_node.inst_name}}':'{{safe_node_name(child_node)}}',
             {%- elif isinstance(child_node, systemrdlMemNode) %}
             '{{child_node.inst_name}}':'{{safe_node_name(child_node)}}',
+            {%- elif isinstance(child_node, systemrdlSignalNode) %}
+            # doing nothing with signal node: {{child_node.inst_name}}
             {% else %}
             {{ raise_template_error('unexpected type') }}
             {%- endif %}

src/peakrdl_python/templates/addrmap_tb.py.jinja

@@ -89,8 +89,12 @@ class {{top_node.type_name}}_TestCase(unittest.TestCase):
         Walk the address map and check the inst name has been correctly populated
         """
         {% for node in top_node.descendants(unroll=True) -%}
+        {% if isinstance(node, systemrdlSignalNode) %}
+        # doing nothing with signal node: {{node.inst_name}}
+        {% else %}
         self.assertEqual(self.dut.{{'.'.join(get_python_path_segments(node))}}.inst_name, '{{node.get_path_segments()[-1]}}')
         self.assertEqual(self.dut.{{'.'.join(get_python_path_segments(node))}}.full_inst_name, '{{'.'.join(node.get_path_segments())}}')
+        {% endif %}
         {% endfor %}
 
     def test_register_properties(self):
@@ -713,8 +717,12 @@ class {{top_node.type_name}}_TestCase(unittest.TestCase):
 
         """
         {%- for node in top_node.descendants(unroll=True) %}
+        {% if isinstance(node, systemrdlSignalNode) %}
+        # doing nothing with signal node: {{node.inst_name}}
+        {% else %}
         with self.assertRaises(AttributeError):
             self.dut.{{'.'.join(get_python_path_segments(node))}}.cppkbrgmgeloagvfgjjeiiushygirh = 1
+        {% endif %}
         {%- endfor %}
 
     {% macro check_readable_register_iterators(node) %}

tests/testcases/bug_81.rdl

@@ -0,0 +1,18 @@
+signal {signalwidth=1; sync; activehigh;} my_signal;
+
+addrmap addrmap_with_signal {
+    default regwidth = 32;
+    default accesswidth = 32;
+
+    signal {signalwidth=1; sync; activehigh;
+    } my_signal;
+
+    reg {
+        default sw = r;
+        default hw = w;
+
+        field {} my_field[32];
+    } my_reg;
+
+    my_reg.my_field->resetsignal = my_signal;
+};