[dual-hart] Investigate why this works in sim but broken on FPGA

[kurtjd]

Unfortunately the dual-hart module seems broken on FPGA, though seems to work fine in simulation. Need to investigate what's up.

[kurtjd]

Made progress in #31, but still hangs. It is likely working in sim because UART TX isn't buffered in the FIFO so we don't need to wait for TX empty interrupt, and thus we are likely experiencing some race or deadlock on FPGA.