Skip to content

Commit 8d243d2

Browse files
povauboinpovauboin
committed
instanciate efinix ip jtag-spi-flash-loader with pin mapping for T8F81
this will likely work also with: FPGA: T4, T8 Package: BGA49, BGA81
0 parents  commit 8d243d2

7 files changed

+4468
-0
lines changed

‎.gitignore‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
.lock
2+
outflow
3+
work_*

‎efx_jtag_spi_flash_loader.peri.xml‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
<?xml version="1.0" encoding="UTF-8"?>
2+
<efxpt:design_db name="efx_jtag_spi_flash_loader" device_def="T8F81" location="/mnt/data/prog/fpga/efx-jtag-spi-flash-loader" version="2022.2.322.1.8" db_version="20222999" last_change_date="Wed Apr 12 17:52:30 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
3+
<efxpt:device_info>
4+
<efxpt:iobank_info>
5+
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
6+
<efxpt:iobank name="1B" iostd="3.3 V LVTTL / LVCMOS"/>
7+
<efxpt:iobank name="1C" iostd="1.1 V"/>
8+
<efxpt:iobank name="2A" iostd="3.3 V LVTTL / LVCMOS"/>
9+
<efxpt:iobank name="2B" iostd="3.3 V LVTTL / LVCMOS"/>
10+
</efxpt:iobank_info>
11+
</efxpt:device_info>
12+
<efxpt:gpio_info device_def="T8F81">
13+
<efxpt:gpio name="ext_clkin" gpio_def="GPIOL_20" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
14+
<efxpt:input_config name="ext_clkin" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
15+
</efxpt:gpio>
16+
<efxpt:gpio name="miso" gpio_def="GPIOL_06" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
17+
<efxpt:input_config name="miso" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
18+
</efxpt:gpio>
19+
<efxpt:gpio name="mosi" gpio_def="GPIOL_04" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
20+
<efxpt:output_config name="mosi" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
21+
</efxpt:gpio>
22+
<efxpt:gpio name="nss" gpio_def="GPIOL_01" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
23+
<efxpt:output_config name="nss" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
24+
</efxpt:gpio>
25+
<efxpt:gpio name="sclk" gpio_def="GPIOL_02" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
26+
<efxpt:output_config name="sclk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="4"/>
27+
</efxpt:gpio>
28+
<efxpt:global_unused_config state="input with weak pullup"/>
29+
</efxpt:gpio_info>
30+
<efxpt:pll_info>
31+
<efxpt:pll name="pll_inst1" pll_def="PLL_0" ref_clock_name="" ref_clock_freq="33.3333" multiplier="72" pre_divider="3" post_divider="1" reset_name="" locked_name="rstn" is_ipfrz="false" is_bypass_lock="true">
32+
<efxpt:output_clock name="clkin" number="0" out_divider="16"/>
33+
</efxpt:pll>
34+
</efxpt:pll_info>
35+
<efxpt:osc_info/>
36+
<efxpt:jtag_info>
37+
<efxpt:jtag name="jtag_inst1" jtag_def="JTAG_USER1">
38+
<efxpt:gen_pin>
39+
<efxpt:pin name="jtag_inst1_DRCK" type_name="DRCK" is_bus="false"/>
40+
<efxpt:pin name="jtag_inst1_TMS" type_name="TMS" is_bus="false"/>
41+
<efxpt:pin name="jtag_inst1_SHIFT" type_name="SHIFT" is_bus="false"/>
42+
<efxpt:pin name="jtag_inst1_TDI" type_name="TDI" is_bus="false"/>
43+
<efxpt:pin name="jtag_inst1_TCK" type_name="TCK" is_bus="false"/>
44+
<efxpt:pin name="jtag_inst1_SEL" type_name="SEL" is_bus="false"/>
45+
<efxpt:pin name="jtag_inst1_RESET" type_name="RESET" is_bus="false"/>
46+
<efxpt:pin name="jtag_inst1_RUNTEST" type_name="RUNTEST" is_bus="false"/>
47+
<efxpt:pin name="jtag_inst1_CAPTURE" type_name="CAPTURE" is_bus="false"/>
48+
<efxpt:pin name="jtag_inst1_UPDATE" type_name="UPDATE" is_bus="false"/>
49+
<efxpt:pin name="jtag_inst1_TDO" type_name="TDO" is_bus="false"/>
50+
</efxpt:gen_pin>
51+
</efxpt:jtag>
52+
</efxpt:jtag_info>
53+
</efxpt:design_db>

‎efx_jtag_spi_flash_loader.sdc‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
# PLL Constraints
2+
#################
3+
create_clock -period 30.00 [get_ports {clkin}]
4+
create_clock -period 100.00 [get_ports {jtag_inst1_TCK}]
5+
6+
# JTAG Constraints
7+
####################
8+
# create_clock -period <USER_PERIOD> [get_ports {jtag_inst1_TCK}]
9+
# create_clock -period <USER_PERIOD> [get_ports {jtag_inst1_DRCK}]
10+
set_output_delay -clock jtag_inst1_TCK -max 0.111 [get_ports {jtag_inst1_TDO}]
11+
set_output_delay -clock jtag_inst1_TCK -min 0.053 [get_ports {jtag_inst1_TDO}]
12+
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.267 [get_ports {jtag_inst1_CAPTURE}]
13+
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.134 [get_ports {jtag_inst1_CAPTURE}]
14+
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.267 [get_ports {jtag_inst1_RESET}]
15+
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.134 [get_ports {jtag_inst1_RESET}]
16+
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.231 [get_ports {jtag_inst1_SEL}]
17+
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.116 [get_ports {jtag_inst1_SEL}]
18+
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.267 [get_ports {jtag_inst1_UPDATE}]
19+
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.134 [get_ports {jtag_inst1_UPDATE}]
20+
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.321 [get_ports {jtag_inst1_SHIFT}]
21+
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.161 [get_ports {jtag_inst1_SHIFT}]

0 commit comments

Comments
 (0)