Sub-project 1: Support for ARM NEON

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• Get to know ISA
• Study programming interface
• prototype float 4
• test float 4
• Coding more data types
  • float 8
  • float 16
• Testing
  • test float 8
  • test float 16

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• Reference
  • NEON - ARM
  • Summary of NEON intrinsics
  • ARM® Compiler toolchain

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• NEON
  • NEON technology is a 128-bit SIMD (Single Instruction, Multiple Data) architecture extension for the ARM Cortex™-A series processors, designed to provide flexible and powerful acceleration for consumer multimedia applications, delivering a significantly enhanced user experience. It has 32 registers, 64-bits wide (dual view as 16 registers, 128-bits wide.
• How to use NEON
  • C intrinsics:
    • C function call interface to NEON operations
    • Supports all data types and operations supported by NEON

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Data Types

• NEON instructions perform "Packed SIMD" processing:
  • Registers are considered as vectors of elements of the same data type
  • Data types can be: signed/unsigned 8-bit, 16-bit, 32-bit, 64-bit, single precision floating point
  • Instructions perform the same operation in all lanes
• Vector data types

Table 43. Vector data types
int8x8_t    int8x16_t
int16x4_t   int16x8_t
int32x2_t   int32x4_t
int64x1_t   int64x2_t
uint8x8_t   uint8x16_t
uint16x4_t  uint16x8_t
uint32x2_t  uint32x4_t
uint64x1_t  uint64x2_t
float16x4_t float16x8_t
float32x2_t float32x4_t
poly8x8_t   poly8x16_t
poly16x4_t  poly16x8_t

    struct int16x4x2_t
    {
        int16x4_t val[2];
    };

• How do I use VRECPE / VRECPEQ for reciprocal estimate?
• ARM® NEON™ Intrinsics Reference IHI0073A_arm_neon_intrinsics_ref.pdf

Double precision support in NEON?

• www.add.ece.ufl.edu/4924/docs/arm/ARM NEON Development.pdf

The NEON subsystem is an advanced SIMD (Single Instruction, Multiple Data) processing unit. This means that it can apply a single type of instruction to many pieces of data at one time in parallel. This is extremely helpful when it comes to media processing such as audio/video filters and codecs.

The NEON system is NOT the floating point unit of the ARM processor. There is separate FPU known as the VFP system. They use the same register space but this is taken care of by the compiler/kernel. There are a few differences between the NEON and VFP systems such as: NEON does not support double-precision floating point numbers, NEON only works on vectors and does not support advanced operations such as square root and divide.

• Cortex-A8 - Texas Instruments Wiki

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Compiling

Dependencies: install package g++-arm-linux-gnueabi gcc-arm-linux-gnueabi under ubuntu

arm-linux-gnueabi-gcc -mcpu=cortex-a8 -mfloat-abi=softfp -mfpu=neon neon.c
arm-linux-gnueabi-g++ -mcpu=cortex-a8 -mfloat-abi=softfp -mfpu=neon neon.cpp

CMake

User choose which vectorization architecture to use

MISC

1. ARM boost Cross Compiling Boost C++ Libraries for ARM
2. CMake Error at /usr/share/cmake-3.2/Modules/FindBoost.cmake:1202 (message):
3. arm_neon.h can use built in GCC allows using the following operators on these types: +, -, *, /, unary minus, ^, |, &, ~, %.
4. typedef __builtin_neon_sf float32x4_t __attribute__ ((__vector_size__ (16))); access elements

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• compile successfully on jetson
  • implement gather, scatter ..
  • include path

cmake -DWITH_CUDA="FALSE" -DADDITIONAL_COMPILE_FLAGS="-D __NEON__ -mfloat-abi=softfp -mfpu=neon" ../
cmake -DWITH_CUDA="FALSE" -DADDITIONAL_COMPILE_FLAGS="-I/usr/include/arm-linux-gnueabihf/c++/4.8/ -D __NEON__ -mfloat-abi=softfp -mfpu=neon" ../
cmake -DADDITIONAL_COMPILE_FLAGS="-mfpu=neon" ../

• non-temporal stores/loads
  • A64 Data Transfer Instructions
  • LDNP, STNP
  • 64bit - For the NEON coding for ARM Arch64,How do you push the registers to the stack??Seems like STMFD is not a part of the instruction set on Arch64? - Stack Overflow
• scatter/gather
  • Coding for NEON - Part 1: Load and Stores
  • Single or Multiple Elements VLD3.8 {d0[3], d1[3], d2[3]}, [r0]
  • only fixed interleaving

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Home > Introducing NEON > NEON architecture overview > NEON registers

1.3.2. NEON registers

The NEON register bank consists of 32 64-bit registers. If both Advanced SIMD and VFPv3 are implemented, they share this register bank. In this case, VFPv3 is implemented in the VFPv3-D32 form t hat supports 32 double-precision floating-point registers. This integration simplifies implementing context switching support, because the same routines that save and restore VFP context also save and restore NEON context.

The NEON unit can view the same register bank as:

• sixteen 128-bit quadword registers, Q0-Q15

• thirty-two 64-bit doubleword registers, D0-D31.

The NEON D0-D31 registers are the same as the VFPv3 D0-D31 registers and each of the Q0-Q15 registers map onto a pair of D registers. Figure 1.3 shows the different views of the shared NEON and VFP register bank. All of these views are accessible at any time. Software does not have to explicitly switch between them, because the instruction used determines the appropriate view.

Figure 1.3. NEON and VFP register set

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// Home > Advanced SIMD and Floating-point Programming (32-bit) > Alignment restrictions in load and store, element and structure instructions
// by the A bit (SCTLR bit[1])

// Home > System Control > AArch32 register descriptions > System Control Register
asm volatile("mrc   p15, 0, r0, c1, c0, 0"); // read SCTLR into r0
asm volatile("orr   r0, r0, #2"); // set SCTLR.A to aligned
asm volatile("mcr   p15, 0, r0, c1, c0, 0"); // write SCTLR

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inaccurate sqrt

• gcc thread Kyrill Tkachov - Re: [PATCH][AArch64] Implement vsqrt_f64 intrinsic
• implementation by WebRTC

inaccurate division

• android - how to divide in neon intrinsics by a float number - Stack Overflow

reciprocal

• How do I use VRECPE / VRECPEQ for reciprocal estimate?
• note: ARM has many documentations .. about many things .. might talk about different versions
• MiKuSite - VFP/NEON stuff