@@ -11,20 +11,7 @@ convergent events.
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This builds on the well-founded ordering relations of Mathlib4,
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which means convergence is not restricted to e.g. natural number
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- of finite set orderings.
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-
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- Technically, anticipated and convergence event specifications depend
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- on a component `variant` of type `v`. For anticipated events, the
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- type `v` must be instance of Mathlib's `Preorder` typeclass, with
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- the usual requirements of preordering: reflexivity and transitivity.
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- For convergent events, the subclass `WellFoundedLT` must also be
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- instantiated, with the main requirement that the "lower than" relation
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- (denoted by `LT.lt` or more simply `·<·`) of the preorder is well-founded.
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- See Mathlib's documentation about these typeclasses for details.
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-
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- *Remark* : One drawback is that Mathlib4 is then a (rather large) dependency
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- but building on such a rich mathematical toolkit is more of an
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- asset than an hindrance.
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+ of finite set orderings (cf. module `Event.Convergent`).
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-/
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@@ -45,7 +32,7 @@ structure _AnticipatedREventPO (v) [Preorder v] [Machine ACTX AM] [Machine CTX
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→ let (_, m') := ev.action m x
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variant m' ≤ variant m
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- /-- The representation of anticipated events, constructed
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+ /-- The representation of anticipated refined events, constructed
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by specifications structures, e.g. `AnticipatedREventSpec`,
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and smart constructors, e.g. `newAnticipatedREvent`. -/
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structure AnticipatedREvent (v) [Preorder v] (AM) [Machine ACTX AM] (M) [Machine CTX M] [instR: Refinement AM M]
@@ -83,6 +70,7 @@ structure AnticipatedREventSpec (v) [Preorder v] (AM) [Machine ACTX AM] (M) [Mac
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{α β α' β'} (abs : OrdinaryEvent AM α' β')
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extends _Variant v, REventSpec AM M (α:=α) (β:=β) (α':=α') (β':=β') abs where
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+ /-- Proof obligation: the variant does not increases. -/
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nonIncreasing (m : M) (x : α):
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Machine.invariant m
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→ guard m x
@@ -152,12 +140,13 @@ private def _newAnticipatedREvent' [Preorder v] [Machine ACTX AM] [Machine CTX M
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(abs : OrdinaryEvent AM α' Unit) (ev : AnticipatedREventSpec' v AM M (α:=α) (α':=α') abs) : AnticipatedREvent v AM M α Unit α' Unit :=
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_newAnticipatedREvent abs ev.toAnticipatedREventSpec
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- /-- Variant of `newAnticipatedREvent ` with implicit `Unit` output type -/
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+ /-- Variant of `newAnticipatedREventFromOrdinary ` with implicit `Unit` output type -/
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@[simp]
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def newAnticipatedREventfromOrdinary' [Preorder v] [Machine ACTX AM] [Machine CTX M] [Refinement AM M]
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(abs : OrdinaryEvent AM α' Unit) (ev : AnticipatedREventSpec' v AM M (α:=α) (α':=α') abs) : AnticipatedREvent v AM M α Unit α' Unit :=
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_newAnticipatedREvent' abs ev
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+ /-- Variant of `newAnticipatedREventFromAnticipated` with implicit `Unit` output type -/
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@[simp]
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def newAnticipatedREventfromAnticipated' [Preorder v] [Machine ACTX AM] [Machine CTX M] [Refinement AM M]
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(abs : AnticipatedEvent v AM α' Unit) (ev : AnticipatedREventSpec' v AM M (α:=α) (α':=α') abs.toOrdinaryEvent) : AnticipatedREvent v AM M α Unit α' Unit :=
@@ -188,12 +177,13 @@ private def _newAnticipatedREvent'' [Preorder v] [Machine ACTX AM] [Machine CTX
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(abs : OrdinaryEvent AM Unit Unit) (ev : AnticipatedREventSpec'' v AM M abs) : AnticipatedREvent v AM M Unit Unit :=
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_newAnticipatedREvent abs ev.toAnticipatedREventSpec
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- /-- Variant of `newAnticipatedREvent ` with implicit `Unit` input and output types -/
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+ /-- Variant of `newAnticipatedREventfromOrdinary ` with implicit `Unit` input and output types -/
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@[simp]
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def newAnticipatedREventfromOrdinary'' [Preorder v] [Machine ACTX AM] [Machine CTX M] [Refinement AM M]
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(abs : OrdinaryEvent AM Unit Unit) (ev : AnticipatedREventSpec'' v AM M abs) : AnticipatedREvent v AM M Unit Unit :=
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_newAnticipatedREvent'' abs ev
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+ /-- Variant of `newAnticipatedREventfromAnticipated` with implicit `Unit` input and output types -/
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@[simp]
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def newAnticipatedREventfromAnticipated'' [Preorder v] [Machine ACTX AM] [Machine CTX M] [Refinement AM M]
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(abs : AnticipatedEvent v AM Unit Unit) (ev : AnticipatedREventSpec'' v AM M abs.toOrdinaryEvent) : AnticipatedREvent v AM M Unit Unit :=
@@ -203,7 +193,7 @@ def newAnticipatedREventfromAnticipated'' [Preorder v] [Machine ACTX AM] [Machin
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### Convergent refined events
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-/
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- /-- Internal representation of proof obligations for events -/
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+ /-- Internal representation of proof obligations for convergent refined events -/
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structure _ConvergentREventPO (v) [Preorder v] [WellFoundedLT v] [Machine ACTX AM] [Machine CTX M] [instR: Refinement AM M]
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(ev : _Event M α β) (kind : EventKind) (α') (β')
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extends _AnticipatedREventPO (instR:=instR) v ev kind α' β' where
@@ -214,7 +204,7 @@ structure _ConvergentREventPO (v) [Preorder v] [WellFoundedLT v] [Machine ACTX A
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→ let (_, m') := ev.action m x
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variant m' < variant m
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- /-- The representation of convergent events, constructed
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+ /-- The representation of convergent refined events, constructed
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by specifications structures, e.g. `ConvergentREventSpec`,
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and smart constructors, e.g. `newConvergentREvent`. -/
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structure ConvergentREvent (v) [Preorder v] [WellFoundedLT v] (AM) [Machine ACTX AM] (M) [Machine CTX M] [instR: Refinement AM M]
@@ -234,7 +224,7 @@ def ConvergentREvent.toConvergentEvent [Preorder v] [WellFoundedLT v] [Machine A
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}
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}
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- /-- Specification of anticipated refined events.
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+ /-- Specification of convergent refined events.
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with: `v` a variant type assumed to be pre-ordered with well-founded less-than relation,
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`AM` the abstact machine type, `M` the concrete maching type,
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`α` the concrete input parameter type, `α'` the corresponding abstract input type (by default, `α`)
@@ -250,6 +240,7 @@ structure ConvergentREventSpec (v) [Preorder v] [WellFoundedLT v] (AM) [Machine
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{α β α' β'} (abs : OrdinaryEvent AM α' β')
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extends _Variant v, REventSpec AM M (α:=α) (β:=β) (α':=α') (β':=β') abs where
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+ /-- Proof obligation: the variant strictly decreases. -/
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convergence (m : M) (x : α):
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Machine.invariant m
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→ guard m x
@@ -258,7 +249,7 @@ structure ConvergentREventSpec (v) [Preorder v] [WellFoundedLT v] (AM) [Machine
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/-- Smart constructor for convergent refined event,
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with: `abs` the event to refine, and
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- `ev` the refined event specification (cf. `AnticipatedREventSpec `).
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+ `ev` the refined event specification (cf. `ConvergentREventSpec `).
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-/
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@[simp]
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def newConvergentREvent [Preorder v] [WellFoundedLT v] [Machine ACTX AM] [Machine CTX M] [Refinement AM M]
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