Skip to content

Commit 0d86c88

Browse files
committed
chore: I need to merge master
1 parent 2cbd3b2 commit 0d86c88

File tree

1 file changed

+33
-26
lines changed
  • src/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations

1 file changed

+33
-26
lines changed

src/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Clz.lean

Lines changed: 33 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -69,74 +69,81 @@ go aig x i acc; where acc = clzAuxRec (i - 1) :=
6969
-- acc n = ite curr [n]
7070
theorem go_denote_base_eq {w : Nat} (aig : AIG α)
7171
(acc : AIG.RefVec aig w) (xc : AIG.RefVec aig w) (x : BitVec w) (assign : α → Bool)
72-
(hc : w ≤ curr)
7372
(hacc : ∀ (idx : Nat) (hidx : idx < w),
7473
⟦aig, acc.get idx hidx, assign⟧
7574
=
7675
(BitVec.clzAuxRec x (w - 1)).getLsbD idx) :
7776
∀ (idx : Nat) (hidx : idx < w),
78-
⟦(go aig xc curr acc).aig, (go aig xc curr acc).vec.get idx hidx, assign⟧ =
77+
⟦(go aig xc w acc).aig, (go aig xc w acc).vec.get idx hidx, assign⟧ =
7978
(BitVec.clzAuxRec x (w - 1)).getLsbD idx := by
8079
intro idx hidx
81-
generalize hgo0 : go aig xc curr acc = res
80+
generalize hgo0 : go aig xc w acc = res
8281
unfold go at hgo0
8382
split at hgo0
8483
· omega
8584
· rw [← hgo0]
8685
simp [hacc]
8786

8887
theorem go_denote_eq {w : Nat} (aig : AIG α)
89-
(acc : AIG.RefVec aig w) (x : AIG.RefVec aig w) (xexpr : BitVec w) (assign : α → Bool)
88+
(acc : AIG.RefVec aig w) (xc : AIG.RefVec aig w) (x : BitVec w) (assign : α → Bool) (hc : curr ≤ w)
9089
-- correctness of the denotation for x and xexpr
91-
(hx : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, x.get idx hidx, assign⟧ = xexpr.getLsbD idx)
90+
(hx : ∀ (idx : Nat) (hidx : idx < w), ⟦aig, xc.get idx hidx, assign⟧ = x.getLsbD idx)
9291
-- correctness of the denotation for the accumulator
9392
(hacc : ∀ (idx : Nat) (hidx : idx < w),
9493
if curr = 0 then ⟦aig, acc.get idx hidx, assign⟧ = (BitVec.ofNat w w).getLsbD idx
95-
else if w ≤ curr then
96-
⟦aig, acc.get idx hidx, assign⟧ = (BitVec.clzAuxRec xexpr (w - 1)).getLsbD idx
97-
else
98-
⟦aig, acc.get idx hidx, assign⟧ = (BitVec.clzAuxRec xexpr (curr - 1)).getLsbD idx)
94+
else ⟦aig, acc.get idx hidx, assign⟧ = (BitVec.clzAuxRec x (curr - 1)).getLsbD idx)
9995
:
10096
∀ (idx : Nat) (hidx : idx < w),
10197
102-
(go aig x curr acc).aig,
103-
(go aig x curr acc).vec.get idx hidx,
98+
(go aig xc curr acc).aig,
99+
(go aig xc curr acc).vec.get idx hidx,
104100
assign
105101
106102
=
107-
(BitVec.clzAuxRec xexpr (w - 1)).getLsbD idx := by
103+
(BitVec.clzAuxRec x (w - 1)).getLsbD idx := by
108104
intro idx hidx
109-
generalize hgo: go aig x curr acc = res
105+
generalize hgo: go aig xc curr acc = res
110106
unfold go at hgo
111107
split at hgo
112-
· -- w < curr
108+
· -- curr < w
113109
case isTrue h =>
114110
simp at hgo
115111
rw [← hgo]
116112
rw [go_denote_eq]
113+
· sorry
117114
· intro idx hidx
118115
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
119116
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastConst)]
120117
simp [hx]
121118
simp [Ref.hgate]
122119
· intro idx hidx
123120
simp [show ¬ curr + 1 = 0 by omega]
124-
by_cases hcw : w ≤ curr + 1
125-
· simp [hcw]
126-
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
127-
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastConst)]
128-
· sorry
129-
· simp [Ref.hgate]
130-
· simp [hcw]
131-
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
132-
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastConst)]
133-
·
134-
sorry
135-
· simp [Ref.hgate]
121+
by_cases hc : curr = 0
122+
· simp [hc] at hacc
123+
simp [hc]
124+
unfold BitVec.clzAuxRec
125+
rw [RefVec.denote_ite (aig := aig)]
126+
by_cases hx0 : x.getLsbD 0
127+
· rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
128+
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastConst)]
129+
· simp [hx0, hacc]
130+
sorry
131+
·
132+
sorry
133+
· rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
134+
rw [AIG.LawfulVecOperator.denote_mem_prefix (f := blastConst)]
135+
· simp [hx0, hacc]
136+
· simp [Ref.hgate]
137+
· simp [hc] at hacc
138+
139+
sorry
136140
· case isFalse h =>
137141
rw [← hgo]
138142
simp [show w ≤ curr by omega, show ¬ curr = 0 by omega] at hacc
139143
simp [hacc]
144+
by_cases hcw : curr = w
145+
· subst hcw; rfl
146+
· omega
140147

141148
-- theorem go_denote_eq {w : Nat} (aig : AIG α) (hw : 0 < w)
142149
-- (acc : AIG.RefVec aig w) (x : AIG.RefVec aig w) (xexpr : BitVec w) (assign : α → Bool)

0 commit comments

Comments
 (0)