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1 parent c0f8c74 commit 8bee481Copy full SHA for 8bee481
src/Init/Data/BitVec/Bitblast.lean
@@ -2192,14 +2192,19 @@ theorem clz_zero : clz 0#w = w := by
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@[simp]
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theorem clz_eq_length_iff {x : BitVec w} :
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clz x = w ↔ x = 0#w := by
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- constructor
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- · intro h
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- have := clz_le (x := x)
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-
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- sorry
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- simp [h, clz_zero]
+ rcases w with _|w
+ · simp [clz, of_length_zero]
+ · constructor
+ · intro h
+ simp [clz] at h
+ have := clzAux_eq_iff (x := x) (n := w)
+ simp [h] at this
+ ext i
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+ simp
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+ apply this
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+ omega
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+ simp [h, clz_zero]
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/--
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preliminary overflow flag for fast umulOverflow circuit
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