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rename hypothesis
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src/Init/Data/BitVec/Bitblast.lean

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1811,7 +1811,7 @@ theorem toNat_pos_of_ne_zero {x : BitVec w} (hx : x ≠ 0#w) :
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omega
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@[simp]
1814-
theorem toInt_umod_neg_add {x y : BitVec w} (humod : ¬y.toInt ∣ x.toInt) (hymsb : y.msb = true) (hxmsb : x.msb = false) :
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theorem toInt_umod_neg_add {x y : BitVec w} (hymsb : y.msb = true) (hxmsb : x.msb = false) (hdvd : ¬y.toInt ∣ x.toInt) :
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(x % -y + y).toInt = x.toInt % y.toInt + y.toInt := by
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rcases w with _|w ; simp [of_length_zero]
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have hypos : 0 < y.toNat := toNat_pos_of_ne_zero (by simp [hymsb])
@@ -1820,16 +1820,16 @@ theorem toInt_umod_neg_add {x y : BitVec w} (humod : ¬y.toInt ∣ x.toInt) (hym
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have hylt : (-y).toNat ≤ 2 ^ (w) := toNat_neg_lt y hymsb
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have hmodlt := Nat.mod_lt x.toNat (y := (-y).toNat)
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(by rw [toNat_neg, Nat.mod_eq_of_lt (by omega)]; omega)
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simp only [humod, reduceIte, toInt_add, hxnonneg, show ¬0 ≤ y.toInt by omega]
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simp only [hdvd, reduceIte, toInt_add, hxnonneg, show ¬0 ≤ y.toInt by omega]
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rw [toInt_umod, toInt_eq_neg_toNat_neg_of_msb_true hymsb, Int.bmod_add_bmod,
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Int.bmod_eq_of_le (n := (x.toNat : Int) % ((-y).toNat : Int) + -((-y).toNat : Int))
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(m := 2 ^ (w+1)) (by omega) (by omega),
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toInt_eq_toNat_of_msb hxmsb, Int.emod_neg]
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@[simp]
1830-
theorem toInt_sub_neg_umod {x y : BitVec (w + 1)} (hxmsb : x.msb = true) (hymsb : y.msb = false)
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(hx_dvd_y : ¬y.toInt ∣ x.toInt) :
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theorem toInt_sub_neg_umod {x y : BitVec w} (hxmsb : x.msb = true) (hymsb : y.msb = false) (hdvd : ¬y.toInt ∣ x.toInt) :
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(y - -x % y).toInt = x.toInt % y.toInt := by
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rcases w with _|w ; simp [of_length_zero]
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have : y.toNat < 2 ^ w := toNat_lt_of_msb_false hymsb
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by_cases hyzero : y = 0#(w+1); subst hyzero; simp
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simp only [toNat_eq, toNat_ofNat, zero_mod] at hyzero
@@ -1839,8 +1839,8 @@ theorem toInt_sub_neg_umod {x y : BitVec (w + 1)} (hxmsb : x.msb = true) (hymsb
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have hmodlt := Nat.mod_lt (x := (-x).toNat) (y := y.toNat) hypos
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rw [Int.bmod_eq_of_le (by omega) (by omega)]
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simp only [toInt_eq_toNat_of_msb hymsb, BitVec.toInt_eq_neg_toNat_neg_of_msb_true hxmsb,
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Int.dvd_neg] at hx_dvd_y
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simp only [hx_dvd_y]
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Int.dvd_neg] at hdvd
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simp only [hdvd]
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simp
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theorem toInt_smod {x y : BitVec w} :

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