@@ -44,15 +44,14 @@ theorem go_denote_eq {w : Nat} (aig : AIG α)
4444 generalize hgo: go aig xc curr acc = res
4545 unfold go at hgo
4646 split at hgo
47- · -- curr < w
48- case isTrue h =>
47+ · case isTrue h =>
4948 simp at hgo
5049 rw [← hgo]
5150 rw [go_denote_eq]
5251 · intro idx hidx
5352 rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
54- simp [hx]
55- simp [Ref.hgate]
53+ · simp [hx]
54+ · simp [Ref.hgate]
5655 · intro idx hidx
5756 simp only [Nat.add_eq_zero, Nat.succ_ne_self, and_false, ↓reduceIte, RefVec.get_cast,
5857 Ref.cast_eq, Nat.add_one_sub_one]
@@ -61,66 +60,56 @@ theorem go_denote_eq {w : Nat} (aig : AIG α)
6160 · case zero =>
6261 split
6362 · next hx' =>
64- have : x.getLsbD 0 = true := by rw [hx] at hx'; exact hx'
65- simp [hacc, BitVec.clzAuxRec, this ]
63+ simp only [BitVec.sub_zero, denote_blastConst, BitVec.clzAuxRec,
64+ show x.getLsbD 0 = true by rw [hx] at hx'; exact hx', ↓reduceIte ]
6665 congr
6766 rw [BitVec.toNat_eq]
6867 rcases w with _|w
6968 · simp
70- · rw [BitVec.ofNat_sub_ofNat, ← BitVec.toNat_eq]
71- rw [← BitVec.ofNat_inj_iff_eq]
69+ · rw [BitVec.ofNat_sub_ofNat]
7270 have hlt := Nat.one_lt_two_pow' w
73- rw [Nat.mod_eq_of_lt hlt]
74- rw [show 2 ^ (w + 1 ) - 1 + (w + 1 ) = 2 ^ (w + 1 ) + w by omega]
71+ rw [Nat.mod_eq_of_lt hlt, show 2 ^ (w + 1 ) - 1 + (w + 1 ) = 2 ^ (w + 1 ) + w by omega]
7572 simp
7673 · next hx' =>
77- have : x.getLsbD 0 = false := by rw [hx ] at hx'; simp at hx'; exact hx'
78- simp [BitVec.clzAuxRec, this]
79- simp at hacc
80- simp [ hacc]
74+ simp only [↓reduceIte ] at hacc
75+ simp only [BitVec.clzAuxRec,
76+ show x.getLsbD 0 = false by rw [hx] at hx'; simp at hx'; exact hx',
77+ Bool.false_eq_true, ↓reduceIte, hacc]
8178 · case succ curr =>
8279 split
8380 · next hx' =>
84- simp at hx'
85- simp [hx']
86- have : x.getLsbD (curr + 1 ) = true := by rw [hx] at hx'; exact hx'
87- simp [hacc, BitVec.clzAuxRec, this]
81+ simp only at hx'
82+ simp only [denote_blastConst,BitVec.clzAuxRec,
83+ show x.getLsbD (curr + 1 ) = true by rw [hx] at hx'; exact hx', ↓reduceIte]
8884 congr
8985 rcases w with _|w
9086 · simp [BitVec.of_length_zero]
9187 · simp [BitVec.ofNat_sub_ofNat, ← BitVec.toNat_eq]
9288 have hlt := Nat.lt_pow_self (n := curr + 1 ) (a := 2 ) (by omega)
93- have hlt := Nat.lt_pow_self (n := w + 1 ) (a := 2 ) (by omega)
9489 have hlt' := Nat.pow_lt_pow_of_lt (a := 2 ) (n := curr + 1 ) (m := w + 1 ) (by omega) (by omega)
95- rw [Nat.mod_eq_of_lt (a := curr + 1 ) (by omega)]
96- rw [show 2 ^ (w + 1 ) - 1 + (w + 1 ) = 2 ^ (w + 1 ) + w by omega, Nat.add_comm]
97- rw [← BitVec.ofNat_inj_iff_eq]
98- rw [Nat.add_comm]
90+ rw [Nat.mod_eq_of_lt (a := curr + 1 ) (by omega),
91+ show 2 ^ (w + 1 ) - 1 + (w + 1 ) = 2 ^ (w + 1 ) + w by omega, Nat.add_comm]
92+ simp only [BitVec.toNat_eq, BitVec.toNat_ofNat]
9993 by_cases hcw : curr + 1 = w
100- · simp [hcw] at *
101- rw [show 2 ^ (1 + w) + w + (2 ^ (1 + w) - w) = 2 ^ (1 + w) +((2 ^ (1 + w) - w) + w) by omega]
102- rw [Nat.add_mod_left]
103- rw [Nat.sub_add_cancel (by rw [Nat.add_comm] at hlt'; omega)]
104- simp
105- · have : curr + 1 < w := by omega
106- have hc2 : curr + 1 < 2 ^ (1 + w) := by
107- rw [Nat.add_comm 1 w]; omega
108- rw [show 2 ^ (1 + w) + w + (2 ^ (1 + w) - (curr + 1 )) = 2 ^ (1 + w) + (2 ^ (1 + w) + (w - (curr + 1 ))) by rw [Nat.add_comm] at hc2; omega]
109- rw [Nat.add_mod_left]
110- rw [Nat.add_mod_left]
94+ · simp only [hcw, Nat.sub_self, Nat.zero_mod] at *
95+ rw [Nat.add_comm,
96+ show 2 ^ (1 + w) + w + (2 ^ (1 + w) - w) = 2 ^ (1 + w) +((2 ^ (1 + w) - w) + w) by omega,
97+ Nat.sub_add_cancel (by rw [Nat.add_comm] at hlt'; omega),
98+ Nat.add_mod_right, Nat.mod_self]
99+ · have hlt'' : curr + 1 < 2 ^ (1 + w) := by rw [Nat.add_comm 1 w]; omega
100+ rw [Nat.add_comm,
101+ show 2 ^ (1 + w) + w + (2 ^ (1 + w) - (curr + 1 )) = 2 ^ (1 + w) + (2 ^ (1 + w) + (w - (curr + 1 ))) by omega,
102+ Nat.add_mod_left, Nat.add_mod_left]
111103 · next hx' =>
112- have : x.getLsbD (curr + 1 ) = false := by rw [hx] at hx'; simp at hx'; exact hx'
113- simp at hx' hacc
114- simp [hx']
115- simp [hacc, BitVec.clzAuxRec, this]
104+ simp only [Nat.add_eq_zero, Nat.succ_ne_self, and_false, ↓reduceIte,
105+ Nat.add_one_sub_one] at hacc
106+ simp [hacc, BitVec.clzAuxRec, show x.getLsbD (curr + 1 ) = false by rw [hx] at hx'; simp at hx'; exact hx']
116107 · case isFalse h =>
117108 rw [← hgo]
118- simp [show w ≤ curr by omega, show ¬ curr = 0 by omega] at hacc
119- simp [hacc]
109+ simp only [show ¬curr = 0 by omega, ↓reduceIte] at hacc
120110 by_cases hcw : curr = w
121- · subst hcw; rfl
122- · rw [BitVec.clzAuxRec_eq_of_le]
123- omega
111+ · subst hcw; simp [hacc]
112+ · simp only [hacc]; rw [BitVec.clzAuxRec_eq_of_le]; omega
124113
125114end blastClz
126115
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