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chore: polish
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  • src/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations

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src/Std/Tactic/BVDecide/Bitblast/BVExpr/Circuit/Lemmas/Operations/Clz.lean

Lines changed: 32 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -44,15 +44,14 @@ theorem go_denote_eq {w : Nat} (aig : AIG α)
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generalize hgo: go aig xc curr acc = res
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unfold go at hgo
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split at hgo
47-
· -- curr < w
48-
case isTrue h =>
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· case isTrue h =>
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simp at hgo
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rw [← hgo]
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rw [go_denote_eq]
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· intro idx hidx
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rw [AIG.LawfulVecOperator.denote_mem_prefix (f := RefVec.ite)]
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simp [hx]
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simp [Ref.hgate]
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· simp [hx]
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· simp [Ref.hgate]
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· intro idx hidx
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simp only [Nat.add_eq_zero, Nat.succ_ne_self, and_false, ↓reduceIte, RefVec.get_cast,
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Ref.cast_eq, Nat.add_one_sub_one]
@@ -61,66 +60,56 @@ theorem go_denote_eq {w : Nat} (aig : AIG α)
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· case zero =>
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split
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· next hx' =>
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have : x.getLsbD 0 = true := by rw [hx] at hx'; exact hx'
65-
simp [hacc, BitVec.clzAuxRec, this]
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simp only [BitVec.sub_zero, denote_blastConst, BitVec.clzAuxRec,
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show x.getLsbD 0 = true by rw [hx] at hx'; exact hx', ↓reduceIte]
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congr
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rw [BitVec.toNat_eq]
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rcases w with _|w
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· simp
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· rw [BitVec.ofNat_sub_ofNat, ← BitVec.toNat_eq]
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rw [← BitVec.ofNat_inj_iff_eq]
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· rw [BitVec.ofNat_sub_ofNat]
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have hlt := Nat.one_lt_two_pow' w
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rw [Nat.mod_eq_of_lt hlt]
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rw [show 2 ^ (w + 1) - 1 + (w + 1) = 2 ^ (w + 1) + w by omega]
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rw [Nat.mod_eq_of_lt hlt, show 2 ^ (w + 1) - 1 + (w + 1) = 2 ^ (w + 1) + w by omega]
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simp
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· next hx' =>
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have : x.getLsbD 0 = false := by rw [hx] at hx'; simp at hx'; exact hx'
78-
simp [BitVec.clzAuxRec, this]
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simp at hacc
80-
simp [hacc]
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simp only [↓reduceIte] at hacc
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simp only [BitVec.clzAuxRec,
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show x.getLsbD 0 = false by rw [hx] at hx'; simp at hx'; exact hx',
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Bool.false_eq_true, ↓reduceIte, hacc]
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· case succ curr =>
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split
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· next hx' =>
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simp at hx'
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simp [hx']
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have : x.getLsbD (curr + 1) = true := by rw [hx] at hx'; exact hx'
87-
simp [hacc, BitVec.clzAuxRec, this]
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simp only at hx'
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simp only [denote_blastConst,BitVec.clzAuxRec,
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show x.getLsbD (curr + 1) = true by rw [hx] at hx'; exact hx', ↓reduceIte]
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congr
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rcases w with _|w
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· simp [BitVec.of_length_zero]
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· simp [BitVec.ofNat_sub_ofNat, ← BitVec.toNat_eq]
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have hlt := Nat.lt_pow_self (n := curr + 1) (a := 2) (by omega)
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have hlt := Nat.lt_pow_self (n := w + 1) (a := 2) (by omega)
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have hlt' := Nat.pow_lt_pow_of_lt (a := 2) (n := curr + 1) (m := w + 1) (by omega) (by omega)
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rw [Nat.mod_eq_of_lt (a := curr + 1) (by omega)]
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rw [show 2 ^ (w + 1) - 1 + (w + 1) = 2 ^ (w + 1) + w by omega, Nat.add_comm]
97-
rw [← BitVec.ofNat_inj_iff_eq]
98-
rw [Nat.add_comm]
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rw [Nat.mod_eq_of_lt (a := curr + 1) (by omega),
91+
show 2 ^ (w + 1) - 1 + (w + 1) = 2 ^ (w + 1) + w by omega, Nat.add_comm]
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simp only [BitVec.toNat_eq, BitVec.toNat_ofNat]
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by_cases hcw : curr + 1 = w
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· simp [hcw] at *
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rw [show 2 ^ (1 + w) + w + (2 ^ (1 + w) - w) = 2 ^ (1 + w) +((2 ^ (1 + w) - w) + w) by omega]
102-
rw [Nat.add_mod_left]
103-
rw [Nat.sub_add_cancel (by rw [Nat.add_comm] at hlt'; omega)]
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simp
105-
· have : curr + 1 < w := by omega
106-
have hc2 : curr + 1 < 2 ^ (1 + w) := by
107-
rw [Nat.add_comm 1 w]; omega
108-
rw [show 2 ^ (1 + w) + w + (2 ^ (1 + w) - (curr + 1)) = 2 ^ (1 + w) + (2 ^ (1 + w) + (w - (curr + 1))) by rw [Nat.add_comm] at hc2; omega]
109-
rw [Nat.add_mod_left]
110-
rw [Nat.add_mod_left]
94+
· simp only [hcw, Nat.sub_self, Nat.zero_mod] at *
95+
rw [Nat.add_comm,
96+
show 2 ^ (1 + w) + w + (2 ^ (1 + w) - w) = 2 ^ (1 + w) +((2 ^ (1 + w) - w) + w) by omega,
97+
Nat.sub_add_cancel (by rw [Nat.add_comm] at hlt'; omega),
98+
Nat.add_mod_right, Nat.mod_self]
99+
· have hlt'' : curr + 1 < 2 ^ (1 + w) := by rw [Nat.add_comm 1 w]; omega
100+
rw [Nat.add_comm,
101+
show 2 ^ (1 + w) + w + (2 ^ (1 + w) - (curr + 1)) = 2 ^ (1 + w) + (2 ^ (1 + w) + (w - (curr + 1))) by omega,
102+
Nat.add_mod_left, Nat.add_mod_left]
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· next hx' =>
112-
have : x.getLsbD (curr + 1) = false := by rw [hx] at hx'; simp at hx'; exact hx'
113-
simp at hx' hacc
114-
simp [hx']
115-
simp [hacc, BitVec.clzAuxRec, this]
104+
simp only [Nat.add_eq_zero, Nat.succ_ne_self, and_false, ↓reduceIte,
105+
Nat.add_one_sub_one] at hacc
106+
simp [hacc, BitVec.clzAuxRec, show x.getLsbD (curr + 1) = false by rw [hx] at hx'; simp at hx'; exact hx']
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· case isFalse h =>
117108
rw [← hgo]
118-
simp [show w ≤ curr by omega, show ¬ curr = 0 by omega] at hacc
119-
simp [hacc]
109+
simp only [show ¬curr = 0 by omega, ↓reduceIte] at hacc
120110
by_cases hcw : curr = w
121-
· subst hcw; rfl
122-
· rw [BitVec.clzAuxRec_eq_of_le]
123-
omega
111+
· subst hcw; simp [hacc]
112+
· simp only [hacc]; rw [BitVec.clzAuxRec_eq_of_le]; omega
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end blastClz
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