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| 1 | +/- |
| 2 | +Copyright (c) 2025 Lean FRO, LLC. or its affiliates. All Rights Reserved. |
| 3 | +Released under Apache 2.0 license as described in the file LICENSE. |
| 4 | +Authors: Kim Morrison |
| 5 | +-/ |
| 6 | +module |
| 7 | + |
| 8 | +prelude |
| 9 | +import Init.Data.Int.Order |
| 10 | + |
| 11 | +namespace Lean.Grind |
| 12 | + |
| 13 | +class NatModule (M : Type u) extends Zero M, Add M, HSMul Nat M M where |
| 14 | + add_zero : ∀ a : M, a + 0 = a |
| 15 | + zero_add : ∀ a : M, 0 + a = a |
| 16 | + add_comm : ∀ a b : M, a + b = b + a |
| 17 | + add_assoc : ∀ a b c : M, a + b + c = a + (b + c) |
| 18 | + zero_smul : ∀ a : M, 0 • a = 0 |
| 19 | + one_smul : ∀ a : M, 1 • a = a |
| 20 | + add_smul : ∀ n m : Nat, ∀ a : M, (n + m) • a = n • a + m • a |
| 21 | + smul_zero : ∀ n : Nat, n • (0 : M) = 0 |
| 22 | + smul_add : ∀ n : Nat, ∀ a b : M, n • (a + b) = n • a + n • b |
| 23 | + mul_smul : ∀ n m : Nat, ∀ a : M, (n * m) • a = n • (m • a) |
| 24 | + |
| 25 | +class IntModule (M : Type u) extends Zero M, Add M, Neg M, Sub M, HSMul Int M M where |
| 26 | + add_zero : ∀ a : M, a + 0 = a |
| 27 | + zero_add : ∀ a : M, 0 + a = a |
| 28 | + add_comm : ∀ a b : M, a + b = b + a |
| 29 | + add_assoc : ∀ a b c : M, a + b + c = a + (b + c) |
| 30 | + zero_smul : ∀ a : M, (0 : Int) • a = 0 |
| 31 | + one_smul : ∀ a : M, (1 : Int) • a = a |
| 32 | + add_smul : ∀ n m : Int, ∀ a : M, (n + m) • a = n • a + m • a |
| 33 | + neg_smul : ∀ n : Int, ∀ a : M, (-n) • a = - (n • a) |
| 34 | + smul_zero : ∀ n : Int, n • (0 : M) = 0 |
| 35 | + smul_add : ∀ n : Int, ∀ a b : M, n • (a + b) = n • a + n • b |
| 36 | + mul_smul : ∀ n m : Int, ∀ a : M, (n * m) • a = n • (m • a) |
| 37 | + neg_add_cancel : ∀ a : M, -a + a = 0 |
| 38 | + sub_eq_add_neg : ∀ a b : M, a - b = a + -b |
| 39 | + |
| 40 | +instance IntModule.toNatModule (M : Type u) [i : IntModule M] : NatModule M := |
| 41 | + { i with |
| 42 | + hSMul a x := (a : Int) • x |
| 43 | + smul_zero := by simp [IntModule.smul_zero] |
| 44 | + add_smul := by simp [IntModule.add_smul] |
| 45 | + smul_add := by simp [IntModule.smul_add] |
| 46 | + mul_smul := by simp [IntModule.mul_smul] } |
| 47 | + |
| 48 | +/-- |
| 49 | +We keep track of rational linear combinations as integer linear combinations, |
| 50 | +but with the assurance that we can cancel the GCD of the coefficients. |
| 51 | +-/ |
| 52 | +class RatModule (M : Type u) extends IntModule M where |
| 53 | + no_int_zero_divisors : ∀ (k : Int) (a : M), k ≠ 0 → k • a = 0 → a = 0 |
| 54 | + |
| 55 | +/-- A preorder is a reflexive, transitive relation `≤` with `a < b` defined in the obvious way. -/ |
| 56 | +class Preorder (α : Type u) extends LE α, LT α where |
| 57 | + le_refl : ∀ a : α, a ≤ a |
| 58 | + le_trans : ∀ a b c : α, a ≤ b → b ≤ c → a ≤ c |
| 59 | + lt := fun a b => a ≤ b ∧ ¬b ≤ a |
| 60 | + lt_iff_le_not_le : ∀ a b : α, a < b ↔ a ≤ b ∧ ¬b ≤ a := by intros; rfl |
| 61 | + |
| 62 | +class IntModule.IsOrdered (M : Type u) [Preorder M] [IntModule M] where |
| 63 | + neg_le_iff : ∀ a b : M, -a ≤ b ↔ -b ≤ a |
| 64 | + neg_lt_iff : ∀ a b : M, -a < b ↔ -b < a |
| 65 | + add_lt_left : ∀ a b c : M, a < b → a + c < b + c |
| 66 | + add_lt_right : ∀ a b c : M, a < b → c + a < c + b |
| 67 | + smul_pos : ∀ (k : Int) (a : M), 0 < a → (0 < k ↔ 0 < k • a) |
| 68 | + smul_neg : ∀ (k : Int) (a : M), a < 0 → (0 < k ↔ k • a < 0) |
| 69 | + smul_nonneg : ∀ (k : Int) (a : M), 0 ≤ a → 0 ≤ k → 0 ≤ k • a |
| 70 | + smul_nonpos : ∀ (k : Int) (a : M), a ≤ 0 → 0 ≤ k → k • a ≤ 0 |
| 71 | + |
| 72 | +end Lean.Grind |
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