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| 1 | +// AVX path (f32x8, 8 lanes) |
| 2 | +// WebAssembly SIMD only supports 128-bit vectors. |
| 3 | +// When compiling AVX intrinsics, Emscripten lowers each 256-bit op into two |
| 4 | +// 128-bit ops. Here we duplicate the lower 128b so result = 2 × SSE (shows |
| 5 | +// upper half is active). |
| 6 | +#include <immintrin.h> |
| 7 | + |
| 8 | +#if !defined(__wasm_simd128__) || !defined(__AVX__) |
| 9 | +#error "Requires -msimd128 and -mavx" |
| 10 | +#endif |
| 11 | + |
| 12 | +float |
| 13 | +simd_avx_add8_sum(float a0, |
| 14 | + float a1, |
| 15 | + float a2, |
| 16 | + float a3, |
| 17 | + float b0, |
| 18 | + float b1, |
| 19 | + float b2, |
| 20 | + float b3) |
| 21 | +{ |
| 22 | + __m256 va = _mm256_set_ps(a3, a2, a1, a0, a3, a2, a1, a0); |
| 23 | + __m256 vb = _mm256_set_ps(b3, b2, b1, b0, b3, b2, b1, b0); |
| 24 | + __m256 vc = _mm256_add_ps(va, vb); |
| 25 | + float out[8]; |
| 26 | + _mm256_storeu_ps(out, vc); |
| 27 | + // Collapse 8-lane vector to scalar for JS/Python assertions |
| 28 | + float s = 0.0f; |
| 29 | + for (int i = 0; i < 8; i++) { |
| 30 | + s += out[i]; |
| 31 | + } |
| 32 | + return s; |
| 33 | +} |
| 34 | + |
| 35 | +float |
| 36 | +simd_avx_dot8(float a0, |
| 37 | + float a1, |
| 38 | + float a2, |
| 39 | + float a3, |
| 40 | + float b0, |
| 41 | + float b1, |
| 42 | + float b2, |
| 43 | + float b3) |
| 44 | +{ |
| 45 | + __m256 va = _mm256_set_ps(a3, a2, a1, a0, a3, a2, a1, a0); |
| 46 | + __m256 vb = _mm256_set_ps(b3, b2, b1, b0, b3, b2, b1, b0); |
| 47 | + __m256 vm = _mm256_mul_ps(va, vb); |
| 48 | + float out[8]; |
| 49 | + _mm256_storeu_ps(out, vm); |
| 50 | + // Collapse 8-lane vector to scalar for JS/Python assertions |
| 51 | + float s = 0.0f; |
| 52 | + for (int i = 0; i < 8; i++) { |
| 53 | + s += out[i]; |
| 54 | + } |
| 55 | + return s; |
| 56 | +} |
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