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Reviewer-Ready English Portfolio Guide - 2026-06-02

Release Scope

This release refreshes lhlizdabezt/embedded-systems-fpga-review-labs for professional portfolio review. It updates the public README, reviewer card, evidence map, contact links, FAQ, local inspection guide, topic guidance, and English release notes.

What Changed

  • Added a complete English reviewer guide aligned with HR, seminar, and engineering review expectations.
  • Added or refreshed assets/reviewer-card.svg with ASCII-safe English text and no moving dotted or curved connector lines.
  • Added structured instructions for review, local inspection, professional boundaries, release usage, and FAQ handling.
  • Standardized public contact links for GitHub, LinkedIn, Facebook, Instagram, YouTube, TikTok, email, and phone.
  • Clarified that public claims are limited to repository-backed evidence.

Reviewer Notes

  • Portfolio track: FPGA, SoPC, Verilog custom IP, Avalon-MM, Nios II C, and lab review evidence.
  • Primary stack: Verilog, Quartus, Platform Designer/Qsys, Avalon-MM, Nios II C, Custom IP, FPGA lab review.
  • Recommended topics: fpga, verilog, sopc, nios-ii, avalon-mm, quartus, platform-designer, embedded-systems, custom-ip, hardware-software.
  • Public language: English (United States).
  • Visual rule: no moving dotted paths, curved connector lines, or text placed behind moving line graphics.

Verification Checklist

  • README headings, captions, labels, and tables are in English.
  • SVG reviewer card uses ASCII-safe English text.
  • Visual evidence is linked from repository-local assets when available.
  • Release page can be used as a stable public review snapshot.
  • Repository topics and description should match the professional summary in this release.