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bug fix for aarch64
1 parent 7d0b4c7 commit 590c9b8

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1 file changed

+14
-21
lines changed

1 file changed

+14
-21
lines changed

remill/Arch/AArch64/Arch.cpp

Lines changed: 14 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -845,11 +845,19 @@ static void AddPCDisp(Instruction &inst, int64_t disp) {
845845
Operand::Address::kAddressCalculation);
846846
}
847847

848-
static void AddNextPC(Instruction &inst) {
848+
static void DecodeFallThroughPC(Instruction &inst) {
849+
Operand not_taken_op = {};
850+
not_taken_op.action = Operand::kActionRead;
851+
not_taken_op.type = Operand::kTypeAddress;
852+
not_taken_op.size = kPCWidth;
853+
not_taken_op.addr.address_size = kPCWidth;
854+
not_taken_op.addr.base_reg.name = "PC";
855+
not_taken_op.addr.base_reg.size = kPCWidth;
856+
not_taken_op.addr.displacement = kInstructionSize;
857+
not_taken_op.addr.kind = Operand::Address::kControlFlowTarget;
858+
inst.operands.push_back(not_taken_op);
849859

850-
// add +4 as the PC displacement
851-
// emit an address computation operand
852-
AddPCDisp(inst, kInstructionSize);
860+
inst.branch_not_taken_pc = inst.next_pc;
853861
}
854862

855863
// Base+offset memory operands are equivalent to indexing into an array.
@@ -1265,7 +1273,7 @@ bool TryDecodeRET_64R_BRANCH_REG(const InstData &data, Instruction &inst) {
12651273
// BLR <Xn>
12661274
bool TryDecodeBLR_64_BRANCH_REG(const InstData &data, Instruction &inst) {
12671275
AddRegOperand(inst, kActionRead, kRegX, kUseAsValue, data.Rn);
1268-
AddNextPC(inst);
1276+
DecodeFallThroughPC(inst);
12691277
return true;
12701278
}
12711279

@@ -1744,21 +1752,6 @@ bool TryDecodeB_ONLY_BRANCH_IMM(const InstData &data, Instruction &inst) {
17441752
return true;
17451753
}
17461754

1747-
static void DecodeFallThroughPC(Instruction &inst) {
1748-
Operand not_taken_op = {};
1749-
not_taken_op.action = Operand::kActionRead;
1750-
not_taken_op.type = Operand::kTypeAddress;
1751-
not_taken_op.size = kPCWidth;
1752-
not_taken_op.addr.address_size = kPCWidth;
1753-
not_taken_op.addr.base_reg.name = "PC";
1754-
not_taken_op.addr.base_reg.size = kPCWidth;
1755-
not_taken_op.addr.displacement = kInstructionSize;
1756-
not_taken_op.addr.kind = Operand::Address::kControlFlowTarget;
1757-
inst.operands.push_back(not_taken_op);
1758-
1759-
inst.branch_not_taken_pc = inst.next_pc;
1760-
}
1761-
17621755
// Decode a relative branch target.
17631756
static void DecodeConditionalBranch(Instruction &inst, int64_t disp) {
17641757

@@ -1848,7 +1841,7 @@ bool TryDecodeBL_ONLY_BRANCH_IMM(const InstData &data, Instruction &inst) {
18481841
(data.imm26.simm26 << 2ULL));
18491842
inst.branch_not_taken_pc = inst.next_pc;
18501843
AddPCDisp(inst, data.imm26.simm26 << 2LL);
1851-
AddNextPC(inst); // Decodes the return address.
1844+
DecodeFallThroughPC(inst); // Decodes the return address.
18521845
return true;
18531846
}
18541847

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