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Issue 150 lift bin dir (#169)
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* Semantics and tests for some of the simd variants of EOR, BIC, BIF, and BIT.

* Minor fix

* Semantics and tests for ADDV.

* Semantics and tests for ADDV, UMINV, UMAXV, SMINV, and SMAXV. Also post-decoders for some fpu simd min/max funcs, but no semantics or tests yet.

* Minor fix.

* Semantics and tests for 32-bit float, reduce-based FMAXV and FMINV. I don't anticipate good results.

* Changes to FMINV and FMAXV. Adds semantics for SMB.

* Semantics and tests for LD1_ASISDLSE_R1_1V, LD1_ASISDLSE_R2_2V, LD1_ASISDLSE_R3_3V, and LD1_ASISDLSE_R4_4V.

* Minor fixes

* First tests for part of LD2.

* Misnamed file

* Rest of the non-postindex LD2 semantics.

* Rest of the non-postindex LD2 semantics.

* Semantics and tests for postindex variants of LD2.

* Minor fixes. This should be the tests and semantics for all LD2 variants.

* Addresses comment
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@pgoodman
pgoodman authored Dec 2, 2017
1 parent 026ea1a commit 885e49d
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Showing 28 changed files with 1,758 additions and 1,107 deletions.
281 changes: 255 additions & 26 deletions remill/Arch/AArch64/Arch.cpp
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1,052 changes: 13 additions & 1,039 deletions remill/Arch/AArch64/Decode.cpp
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20 changes: 13 additions & 7 deletions remill/Arch/AArch64/Decode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2312,6 +2312,12 @@ union InstImm {
} __attribute__((packed));
static_assert(sizeof(InstImm) == 8, "");

#ifdef REMILL_AARCH_STRICT_REGNUM
enum class RegNum : uint8_t;
#else
using RegNum = uint8_t;
#endif

struct InstData {
InstForm iform;
InstName iclass;
Expand All @@ -2338,13 +2344,13 @@ struct InstData {
uint8_t opcode; // LD3_asisdlsop_DX3_r3d, ...
uint8_t opcode2; // UDIV_64_dp_2src, ...
uint8_t scale; // UCVTF_D64_float2fix, ...
uint8_t Ra; // FNMADD_D_floatdp3, ...
uint8_t Rd; // ORN_64_log_shift, ...
uint8_t Rm; // ORN_64_log_shift, ...
uint8_t Rn; // LDCLRLB_32_memop, ...
uint8_t Rs; // LDCLRLB_32_memop, ...
uint8_t Rt; // LDCLRLB_32_memop, ...
uint8_t Rt2; // STP_64_ldstpair_off, ...
RegNum Ra; // FNMADD_D_floatdp3, ...
RegNum Rd; // ORN_64_log_shift, ...
RegNum Rm; // ORN_64_log_shift, ...
RegNum Rn; // LDCLRLB_32_memop, ...
RegNum Rs; // LDCLRLB_32_memop, ...
RegNum Rt; // LDCLRLB_32_memop, ...
RegNum Rt2; // STP_64_ldstpair_off, ...
uint8_t b40; // TBZ_only_testbranch, ...
uint8_t op2; // EXT_asimdext_only, ...
uint8_t op4; // RET_64R_branch_reg, ...
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230 changes: 210 additions & 20 deletions remill/Arch/AArch64/Semantics/DATAXFER.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -655,12 +655,150 @@ DEF_ISEL(LDAR_LR64_LDSTEXCL) = LoadAcquire<R64W, M64>;

namespace {

#define MAKE_LD1(esize) \
template <typename S> \
DEF_SEM(LD1_SINGLE_ ## esize, V128W dst1, S src) { \
auto elems1 = UReadV ## esize(src); \
UWriteV ## esize(dst1, elems1); \
return memory; \
}

MAKE_LD1(8)
MAKE_LD1(16)
MAKE_LD1(32)
MAKE_LD1(64)

#undef MAKE_LD1

} // namespace

DEF_ISEL(LD1_ASISDLSE_R1_1V_8B) = LD1_SINGLE_8<MV64>;
DEF_ISEL(LD1_ASISDLSE_R1_1V_16B) = LD1_SINGLE_8<MV128>;

DEF_ISEL(LD1_ASISDLSE_R1_1V_4H) = LD1_SINGLE_16<MV64>;
DEF_ISEL(LD1_ASISDLSE_R1_1V_8H) = LD1_SINGLE_16<MV128>;

DEF_ISEL(LD1_ASISDLSE_R1_1V_2S) = LD1_SINGLE_32<MV64>;
DEF_ISEL(LD1_ASISDLSE_R1_1V_4S) = LD1_SINGLE_32<MV128>;

DEF_ISEL(LD1_ASISDLSE_R1_1V_1D) = LD1_SINGLE_64<MV64>;
DEF_ISEL(LD1_ASISDLSE_R1_1V_2D) = LD1_SINGLE_64<MV128>;

namespace {

#define MAKE_LD1(esize) \
template <typename S> \
DEF_SEM(LD1_PAIR_ ## esize, V128W dst1, V128W dst2, S src) { \
auto elems1 = UReadV ## esize(src); \
auto elems2 = UReadV ## esize(GetElementPtr(src, 1U)); \
UWriteV ## esize(dst1, elems1); \
UWriteV ## esize(dst2, elems2); \
return memory; \
}

MAKE_LD1(8)
MAKE_LD1(16)
MAKE_LD1(32)
MAKE_LD1(64)

#undef MAKE_LD1

} // namespace

DEF_ISEL(LD1_ASISDLSE_R2_2V_8B) = LD1_PAIR_8<MV64>;
DEF_ISEL(LD1_ASISDLSE_R2_2V_16B) = LD1_PAIR_8<MV128>;

DEF_ISEL(LD1_ASISDLSE_R2_2V_4H) = LD1_PAIR_16<MV64>;
DEF_ISEL(LD1_ASISDLSE_R2_2V_8H) = LD1_PAIR_16<MV128>;

DEF_ISEL(LD1_ASISDLSE_R2_2V_2S) = LD1_PAIR_32<MV64>;
DEF_ISEL(LD1_ASISDLSE_R2_2V_4S) = LD1_PAIR_32<MV128>;

DEF_ISEL(LD1_ASISDLSE_R2_2V_1D) = LD1_PAIR_64<MV64>;
DEF_ISEL(LD1_ASISDLSE_R2_2V_2D) = LD1_PAIR_64<MV128>;


namespace {

#define MAKE_LD1(esize) \
template <typename S> \
DEF_SEM(LD1_TRIPLE_ ## esize, V128W dst1, V128W dst2, \
V128W dst3, S src) { \
auto elems1 = UReadV ## esize(src); \
auto elems2 = UReadV ## esize(GetElementPtr(src, 1U)); \
auto elems3 = UReadV ## esize(GetElementPtr(src, 2U)); \
UWriteV ## esize(dst1, elems1); \
UWriteV ## esize(dst2, elems2); \
UWriteV ## esize(dst3, elems3); \
return memory; \
}

MAKE_LD1(8)
MAKE_LD1(16)
MAKE_LD1(32)
MAKE_LD1(64)

#undef MAKE_LD1

} // namespace

DEF_ISEL(LD1_ASISDLSE_R3_3V_8B) = LD1_TRIPLE_8<MV64>;
DEF_ISEL(LD1_ASISDLSE_R3_3V_16B) = LD1_TRIPLE_8<MV128>;

DEF_ISEL(LD1_ASISDLSE_R3_3V_4H) = LD1_TRIPLE_16<MV64>;
DEF_ISEL(LD1_ASISDLSE_R3_3V_8H) = LD1_TRIPLE_16<MV128>;

DEF_ISEL(LD1_ASISDLSE_R3_3V_2S) = LD1_TRIPLE_32<MV64>;
DEF_ISEL(LD1_ASISDLSE_R3_3V_4S) = LD1_TRIPLE_32<MV128>;

DEF_ISEL(LD1_ASISDLSE_R3_3V_1D) = LD1_TRIPLE_64<MV64>;
DEF_ISEL(LD1_ASISDLSE_R3_3V_2D) = LD1_TRIPLE_64<MV128>;

namespace {

#define MAKE_LD1(esize) \
template <typename S> \
DEF_SEM(LD1_QUAD_ ## esize, V128W dst1, V128W dst2, \
V128W dst3, V128W dst4, S src) { \
auto elems1 = UReadV ## esize(src); \
auto elems2 = UReadV ## esize(GetElementPtr(src, 1U)); \
auto elems3 = UReadV ## esize(GetElementPtr(src, 2U)); \
auto elems4 = UReadV ## esize(GetElementPtr(src, 3U)); \
UWriteV ## esize(dst1, elems1); \
UWriteV ## esize(dst2, elems2); \
UWriteV ## esize(dst3, elems3); \
UWriteV ## esize(dst4, elems4); \
return memory; \
}

MAKE_LD1(8)
MAKE_LD1(16)
MAKE_LD1(32)
MAKE_LD1(64)

#undef MAKE_LD1

} // namespace

DEF_ISEL(LD1_ASISDLSE_R4_4V_8B) = LD1_QUAD_8<MV64>;
DEF_ISEL(LD1_ASISDLSE_R4_4V_16B) = LD1_QUAD_8<MV128>;

DEF_ISEL(LD1_ASISDLSE_R4_4V_4H) = LD1_QUAD_16<MV64>;
DEF_ISEL(LD1_ASISDLSE_R4_4V_8H) = LD1_QUAD_16<MV128>;

DEF_ISEL(LD1_ASISDLSE_R4_4V_2S) = LD1_QUAD_32<MV64>;
DEF_ISEL(LD1_ASISDLSE_R4_4V_4S) = LD1_QUAD_32<MV128>;

DEF_ISEL(LD1_ASISDLSE_R4_4V_1D) = LD1_QUAD_64<MV64>;
DEF_ISEL(LD1_ASISDLSE_R4_4V_2D) = LD1_QUAD_64<MV128>;

namespace {

#define MAKE_LD1_POSTINDEX(esize) \
template <typename S> \
DEF_SEM(LD1_SINGLE_POSTINDEX_ ## esize, V128W dst1, S src, \
R64W addr_reg, ADDR next_addr) { \
auto elems1 = UReadV ## esize(src); \
UWriteV ## esize(dst1, elems1); \
memory = LD1_SINGLE_ ## esize(memory, state, dst1, src); \
Write(addr_reg, Read(next_addr)); \
return memory; \
}
Expand Down Expand Up @@ -692,10 +830,7 @@ namespace {
template <typename S> \
DEF_SEM(LD1_PAIR_POSTINDEX_ ## esize, V128W dst1, V128W dst2, S src, \
R64W addr_reg, ADDR next_addr) { \
auto elems1 = UReadV ## esize(src); \
auto elems2 = UReadV ## esize(GetElementPtr(src, 1U)); \
UWriteV ## esize(dst1, elems1); \
UWriteV ## esize(dst2, elems2); \
memory = LD1_PAIR_ ## esize(memory, state, dst1, dst2, src); \
Write(addr_reg, Read(next_addr)); \
return memory; \
}
Expand Down Expand Up @@ -727,12 +862,7 @@ namespace {
template <typename S> \
DEF_SEM(LD1_TRIPLE_POSTINDEX_ ## esize, V128W dst1, V128W dst2, \
V128W dst3, S src, R64W addr_reg, ADDR next_addr) { \
auto elems1 = UReadV ## esize(src); \
auto elems2 = UReadV ## esize(GetElementPtr(src, 1U)); \
auto elems3 = UReadV ## esize(GetElementPtr(src, 2U)); \
UWriteV ## esize(dst1, elems1); \
UWriteV ## esize(dst2, elems2); \
UWriteV ## esize(dst3, elems3); \
memory = LD1_TRIPLE_ ## esize(memory, state, dst1, dst2, dst3, src); \
Write(addr_reg, Read(next_addr)); \
return memory; \
}
Expand Down Expand Up @@ -764,14 +894,7 @@ namespace {
template <typename S> \
DEF_SEM(LD1_QUAD_POSTINDEX_ ## esize, V128W dst1, V128W dst2, \
V128W dst3, V128W dst4, S src, R64W addr_reg, ADDR next_addr) { \
auto elems1 = UReadV ## esize(src); \
auto elems2 = UReadV ## esize(GetElementPtr(src, 1U)); \
auto elems3 = UReadV ## esize(GetElementPtr(src, 2U)); \
auto elems4 = UReadV ## esize(GetElementPtr(src, 3U)); \
UWriteV ## esize(dst1, elems1); \
UWriteV ## esize(dst2, elems2); \
UWriteV ## esize(dst3, elems3); \
UWriteV ## esize(dst4, elems4); \
memory = LD1_QUAD_ ## esize(memory, state, dst1, dst2, dst3, dst4, src); \
Write(addr_reg, Read(next_addr)); \
return memory; \
}
Expand Down Expand Up @@ -799,6 +922,73 @@ DEF_ISEL(LD1_ASISDLSEP_I4_I4_2D) = LD1_QUAD_POSTINDEX_64<MV128>;

namespace {

#define MAKE_LD2(size) \
template <typename S> \
DEF_SEM(LD2_ ## size, V128W dst1, V128W dst2, S src) { \
auto vec = UReadV ## size(src); \
auto dst1_vec = UClearV ## size(UReadV ## size(dst1)); \
auto dst2_vec = UClearV ## size(UReadV ## size(dst2)); \
_Pragma("unroll") \
for (size_t i = 0, j = 0; i < NumVectorElems(vec); j++) { \
dst1_vec = UInsertV ## size(dst1_vec, j, UExtractV ## size(vec, i++)); \
dst2_vec = UInsertV ## size(dst2_vec, j, UExtractV ## size(vec, i++)); \
} \
UWriteV ## size(dst1, dst1_vec); \
UWriteV ## size(dst2, dst2_vec); \
return memory; \
}

MAKE_LD2(8)
MAKE_LD2(16)
MAKE_LD2(32)
MAKE_LD2(64)

#undef MAKE_LD2

#define MAKE_LD2(size) \
template <typename S> \
DEF_SEM(LD2_ ## size ## _POSTINDEX, V128W dst1, V128W dst2, S src, \
R64W addr_reg, ADDR next_addr) { \
memory = LD2_ ## size(memory, state, dst1, dst2, src); \
Write(addr_reg, Read(next_addr)); \
return memory; \
}

MAKE_LD2(8)
MAKE_LD2(16)
MAKE_LD2(32)
MAKE_LD2(64)

#undef MAKE_LD2

} // namespace

DEF_ISEL(LD2_ASISDLSE_R2_8B) = LD2_8<MV128>;
DEF_ISEL(LD2_ASISDLSE_R2_16B) = LD2_8<MV256>;
DEF_ISEL(LD2_ASISDLSE_R2_4H) = LD2_16<MV128>;
DEF_ISEL(LD2_ASISDLSE_R2_8H) = LD2_16<MV256>;
DEF_ISEL(LD2_ASISDLSE_R2_2S) = LD2_32<MV128>;
DEF_ISEL(LD2_ASISDLSE_R2_4S) = LD2_32<MV256>;
DEF_ISEL(LD2_ASISDLSE_R2_2D) = LD2_64<MV256>;

DEF_ISEL(LD2_ASISDLSEP_I2_I_8B) = LD2_8_POSTINDEX<MV128>;
DEF_ISEL(LD2_ASISDLSEP_I2_I_16B) = LD2_8_POSTINDEX<MV256>;
DEF_ISEL(LD2_ASISDLSEP_I2_I_4H) = LD2_16_POSTINDEX<MV128>;
DEF_ISEL(LD2_ASISDLSEP_I2_I_8H) = LD2_16_POSTINDEX<MV256>;
DEF_ISEL(LD2_ASISDLSEP_I2_I_2S) = LD2_32_POSTINDEX<MV128>;
DEF_ISEL(LD2_ASISDLSEP_I2_I_4S) = LD2_32_POSTINDEX<MV256>;
DEF_ISEL(LD2_ASISDLSEP_I2_I_2D) = LD2_64_POSTINDEX<MV256>;

DEF_ISEL(LD2_ASISDLSEP_R2_R_8B) = LD2_8_POSTINDEX<MV128>;
DEF_ISEL(LD2_ASISDLSEP_R2_R_16B) = LD2_8_POSTINDEX<MV256>;
DEF_ISEL(LD2_ASISDLSEP_R2_R_4H) = LD2_16_POSTINDEX<MV128>;
DEF_ISEL(LD2_ASISDLSEP_R2_R_8H) = LD2_16_POSTINDEX<MV256>;
DEF_ISEL(LD2_ASISDLSEP_R2_R_2S) = LD2_32_POSTINDEX<MV128>;
DEF_ISEL(LD2_ASISDLSEP_R2_R_4S) = LD2_32_POSTINDEX<MV256>;
DEF_ISEL(LD2_ASISDLSEP_R2_R_2D) = LD2_64_POSTINDEX<MV256>;

namespace {

#define EXTRACT_VEC(prefix, size, ext_op) \
template <typename D, typename T> \
DEF_SEM(prefix ## MovFromVec ## size, D dst, V128 src, I64 index) { \
Expand Down
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