From 99df2e19d4c4af677948a851461e9ffb3c164331 Mon Sep 17 00:00:00 2001 From: Peter Goodman Date: Wed, 5 Aug 2020 15:42:25 -0400 Subject: [PATCH] =?UTF-8?q?Running=20clang-format=20on=20files=20with=20so?= =?UTF-8?q?me=20additional=20custom=20scripts=20for=E2=80=A6=20(#444)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Running clang-format on files with some additional custom scripts for my style * Fix missing unique_ptr in remill/BC/Optimizer.h * Fixes and selective disabling of clang-format --- .clang-format | 151 +- remill/Arch/AArch64/Arch.cpp | 479 +- remill/Arch/AArch64/Decode.cpp | 3172 +- remill/Arch/AArch64/Decode.h | 63 +- remill/Arch/AArch64/Extract.cpp | 60504 +++++++++-------- remill/Arch/AArch64/Runtime/BasicBlock.cpp | 8 +- remill/Arch/AArch64/Runtime/Instructions.cpp | 13 +- remill/Arch/AArch64/Runtime/State.h | 102 +- remill/Arch/AArch64/Semantics/BINARY.cpp | 8 +- remill/Arch/AArch64/Semantics/BITBYTE.cpp | 22 +- remill/Arch/AArch64/Semantics/BRANCH.cpp | 1 - remill/Arch/AArch64/Semantics/COND.cpp | 53 +- remill/Arch/AArch64/Semantics/CONVERT.cpp | 3 +- remill/Arch/AArch64/Semantics/DATAXFER.cpp | 390 +- remill/Arch/AArch64/Semantics/FLAGS.cpp | 81 +- remill/Arch/AArch64/Semantics/LOGICAL.cpp | 4 +- remill/Arch/AArch64/Semantics/SIMD.cpp | 290 +- remill/Arch/AArch64/Semantics/SYSTEM.cpp | 7 +- remill/Arch/Arch.cpp | 398 +- remill/Arch/Arch.h | 58 +- remill/Arch/Float.h | 24 +- remill/Arch/Instruction.cpp | 127 +- remill/Arch/Instruction.h | 30 +- remill/Arch/Name.cpp | 36 +- remill/Arch/Name.h | 42 +- remill/Arch/Runtime/Definitions.h | 201 +- remill/Arch/Runtime/Intrinsics.cpp | 9 +- remill/Arch/Runtime/Intrinsics.h | 287 +- remill/Arch/Runtime/Operators.h | 1133 +- remill/Arch/Runtime/Runtime.h | 4 +- remill/Arch/Runtime/Types.h | 203 +- remill/Arch/X86/Arch.cpp | 304 +- remill/Arch/X86/Runtime/BasicBlock.cpp | 22 +- remill/Arch/X86/Runtime/Instructions.cpp | 56 +- remill/Arch/X86/Runtime/Operators.h | 33 +- remill/Arch/X86/Runtime/State.h | 403 +- remill/Arch/X86/Runtime/Types.h | 11 +- remill/Arch/X86/Semantics/AVX.cpp | 11 +- remill/Arch/X86/Semantics/BINARY.cpp | 192 +- remill/Arch/X86/Semantics/BITBYTE.cpp | 21 +- remill/Arch/X86/Semantics/CALL_RET.cpp | 14 +- remill/Arch/X86/Semantics/CMOV.cpp | 36 +- remill/Arch/X86/Semantics/COND_BR.cpp | 66 +- remill/Arch/X86/Semantics/CONVERT.cpp | 94 +- remill/Arch/X86/Semantics/DATAXFER.cpp | 154 +- remill/Arch/X86/Semantics/DECIMAL.cpp | 2 +- remill/Arch/X86/Semantics/FLAGOP.cpp | 16 +- remill/Arch/X86/Semantics/FLAGS.cpp | 113 +- remill/Arch/X86/Semantics/FMA.cpp | 20 +- remill/Arch/X86/Semantics/IO.cpp | 24 +- remill/Arch/X86/Semantics/LOGICAL.cpp | 104 +- remill/Arch/X86/Semantics/MISC.cpp | 28 +- remill/Arch/X86/Semantics/MMX.cpp | 645 +- remill/Arch/X86/Semantics/NOP.cpp | 2 +- remill/Arch/X86/Semantics/POP.cpp | 34 +- remill/Arch/X86/Semantics/PUSH.cpp | 7 +- remill/Arch/X86/Semantics/ROTATE.cpp | 52 +- remill/Arch/X86/Semantics/RTM.cpp | 3 +- remill/Arch/X86/Semantics/SEMAPHORE.cpp | 25 +- remill/Arch/X86/Semantics/SHIFT.cpp | 9 +- remill/Arch/X86/Semantics/SSE.cpp | 601 +- remill/Arch/X86/Semantics/STRINGOP.cpp | 264 +- remill/Arch/X86/Semantics/SYSTEM.cpp | 97 +- remill/Arch/X86/Semantics/X87.cpp | 157 +- remill/Arch/X86/Semantics/XSAVE.cpp | 4 +- remill/Arch/X86/XED.h | 1 - remill/BC/Annotate.cpp | 52 +- remill/BC/Annotate.h | 208 +- remill/BC/Compat/BitcodeReaderWriter.h | 6 +- remill/BC/Compat/DataLayout.h | 4 +- remill/BC/Compat/DebugInfo.h | 4 +- remill/BC/Compat/Error.h | 15 +- remill/BC/Compat/FileSystem.h | 2 +- remill/BC/Compat/GlobalValue.h | 4 +- remill/BC/Compat/IRReader.h | 8 +- remill/BC/Compat/JITSymbol.h | 4 +- remill/BC/Compat/RuntimeDyld.h | 6 +- remill/BC/Compat/ScalarTransforms.h | 6 +- remill/BC/Compat/TargetLibraryInfo.h | 4 +- remill/BC/Compat/ToolOutputFile.h | 3 +- remill/BC/Compat/Verifier.h | 4 +- remill/BC/DeadStoreEliminator.cpp | 353 +- remill/BC/DeadStoreEliminator.h | 11 +- remill/BC/IntrinsicTable.cpp | 53 +- remill/BC/IntrinsicTable.h | 60 +- remill/BC/Lifter.cpp | 348 +- remill/BC/Lifter.h | 60 +- remill/BC/Optimizer.cpp | 30 +- remill/BC/Optimizer.h | 203 +- remill/BC/Util.cpp | 444 +- remill/BC/Util.h | 90 +- remill/BC/Version.h | 234 +- remill/OS/Compat.cpp | 42 +- remill/OS/FileSystem.cpp | 100 +- remill/OS/OS.cpp | 52 +- remill/OS/OS.h | 63 +- scripts/format-added-files | 58 + scripts/format-files | 193 + tests/AArch64/Lift.cpp | 57 +- tests/AArch64/Run.cpp | 202 +- tests/AArch64/Test.h | 10 +- tests/X86/Lift.cpp | 35 +- tests/X86/PrintSaveState.cpp | 369 +- tests/X86/Run.cpp | 316 +- tests/X86/Test.h | 10 +- tools/CMakeLists.txt | 6 +- tools/lift/Lift.cpp | 127 +- 107 files changed, 38140 insertions(+), 37244 deletions(-) create mode 100755 scripts/format-added-files create mode 100755 scripts/format-files diff --git a/.clang-format b/.clang-format index 981a0d287..5d75fab20 100644 --- a/.clang-format +++ b/.clang-format @@ -1,96 +1,69 @@ --- -Language: Cpp -# BasedOnStyle: Google -AccessModifierOffset: -1 +BasedOnStyle: Google +AccessModifierOffset: '-1' AlignAfterOpenBracket: Align -AlignConsecutiveAssignments: false -AlignConsecutiveDeclarations: false -AlignEscapedNewlinesLeft: true -AlignOperands: true -AlignTrailingComments: true -AllowAllParametersOfDeclarationOnNextLine: true -AllowShortBlocksOnASingleLine: false -AllowShortCaseLabelsOnASingleLine: false -AllowShortFunctionsOnASingleLine: All -AllowShortIfStatementsOnASingleLine: true -AllowShortLoopsOnASingleLine: true -AlwaysBreakAfterDefinitionReturnType: None +AlignConsecutiveMacros: 'false' +AlignConsecutiveAssignments: 'false' +AlignConsecutiveDeclarations: 'false' +AlignEscapedNewlines: DontAlign +AlignOperands: 'true' +AlignTrailingComments: 'false' +AllowAllArgumentsOnNextLine: 'true' +AllowAllConstructorInitializersOnNextLine: 'false' +AllowAllParametersOfDeclarationOnNextLine: 'true' +AllowShortBlocksOnASingleLine: 'false' +AllowShortCaseLabelsOnASingleLine: 'true' +AllowShortFunctionsOnASingleLine: Empty +AllowShortIfStatementsOnASingleLine: Never +AllowShortLambdasOnASingleLine: All +AllowShortLoopsOnASingleLine: 'false' AlwaysBreakAfterReturnType: None -AlwaysBreakBeforeMultilineStrings: true -AlwaysBreakTemplateDeclarations: true -BinPackArguments: true -BinPackParameters: true -BraceWrapping: - AfterClass: false - AfterControlStatement: false - AfterEnum: false - AfterFunction: false - AfterNamespace: false - AfterObjCDeclaration: false - AfterStruct: false - AfterUnion: false - BeforeCatch: false - BeforeElse: false - IndentBraces: false +AlwaysBreakTemplateDeclarations: 'Yes' +BinPackParameters: 'true' BreakBeforeBinaryOperators: None -BreakBeforeBraces: Attach -BreakBeforeTernaryOperators: true -BreakConstructorInitializersBeforeComma: false -BreakAfterJavaFieldAnnotations: false -BreakStringLiterals: true -ColumnLimit: 80 -CommentPragmas: '^ IWYU pragma:' -ConstructorInitializerAllOnOneLineOrOnePerLine: true -ConstructorInitializerIndentWidth: 4 -ContinuationIndentWidth: 4 -Cpp11BracedListStyle: true -DerivePointerAlignment: true -DisableFormat: false -ExperimentalAutoDetectBinPacking: false -ForEachMacros: [ foreach, Q_FOREACH, BOOST_FOREACH ] -IncludeCategories: - - Regex: '^<.*\.h>' - Priority: 1 - - Regex: '^<.*' - Priority: 2 - - Regex: '.*' - Priority: 3 -IncludeIsMainRegex: '([-_](test|unittest))?$' -IndentCaseLabels: true -IndentWidth: 2 -IndentWrappedFunctionNames: false -JavaScriptQuotes: Leave -JavaScriptWrapImports: true -KeepEmptyLinesAtTheStartOfBlocks: false -MacroBlockBegin: '' -MacroBlockEnd: '' -MaxEmptyLinesToKeep: 1 +BreakBeforeBraces: Custom +BreakConstructorInitializers: BeforeColon +BreakInheritanceList: BeforeColon +BreakStringLiterals: 'false' +ColumnLimit: '80' +CompactNamespaces: 'false' +ConstructorInitializerAllOnOneLineOrOnePerLine: 'true' +ConstructorInitializerIndentWidth: '4' +ContinuationIndentWidth: '4' +Cpp11BracedListStyle: 'true' +DerivePointerAlignment: 'false' +FixNamespaceComments: 'true' +IncludeBlocks: Regroup +IndentCaseLabels: 'true' +IndentPPDirectives: AfterHash +IndentWidth: '2' +IndentWrappedFunctionNames: 'false' +KeepEmptyLinesAtTheStartOfBlocks: 'true' +Language: Cpp +MaxEmptyLinesToKeep: '2' NamespaceIndentation: None -ObjCBlockIndentWidth: 2 -ObjCSpaceAfterProperty: false -ObjCSpaceBeforeProtocolList: false -PenaltyBreakBeforeFirstCallParameter: 1 -PenaltyBreakComment: 300 -PenaltyBreakFirstLessLess: 120 -PenaltyBreakString: 1000 -PenaltyExcessCharacter: 1000000 -PenaltyReturnTypeOnItsOwnLine: 200 -PointerAlignment: Left -ReflowComments: true -SortIncludes: true -SpaceAfterCStyleCast: false -SpaceAfterTemplateKeyword: true -SpaceBeforeAssignmentOperators: true +PointerAlignment: Right +ReflowComments: 'false' +SortIncludes: 'true' +SortUsingDeclarations: 'true' +SpaceAfterCStyleCast: 'true' +SpaceAfterLogicalNot: 'false' +SpaceAfterTemplateKeyword: 'true' +SpaceBeforeAssignmentOperators: 'true' +SpaceBeforeCtorInitializerColon: 'true' +SpaceBeforeInheritanceColon: 'true' SpaceBeforeParens: ControlStatements -SpaceInEmptyParentheses: false -SpacesBeforeTrailingComments: 2 -SpacesInAngles: false -SpacesInContainerLiterals: true -SpacesInCStyleCastParentheses: false -SpacesInParentheses: false -SpacesInSquareBrackets: false -Standard: Auto -TabWidth: 2 -UseTab: Never -... +SpaceBeforeRangeBasedForLoopColon: 'true' +SpaceInEmptyParentheses: 'false' +SpacesBeforeTrailingComments: '2' +SpacesInAngles: 'false' +SpacesInCStyleCastParentheses: 'false' +SpacesInContainerLiterals: 'false' +SpacesInParentheses: 'false' +SpacesInSquareBrackets: 'false' +Standard: Cpp11 +TabWidth: '2' +UseTab: Never +PenaltyReturnTypeOnItsOwnLine: '40' +... diff --git a/remill/Arch/AArch64/Arch.cpp b/remill/Arch/AArch64/Arch.cpp index bfa85322e..f15b58896 100644 --- a/remill/Arch/AArch64/Arch.cpp +++ b/remill/Arch/AArch64/Arch.cpp @@ -16,6 +16,10 @@ #include #include +#include +#include +#include +#include #include #include @@ -25,11 +29,6 @@ #include #include -#include -#include -#include -#include - #define REMILL_AARCH_STRICT_REGNUM #include "remill/Arch/AArch64/Decode.h" @@ -52,8 +51,7 @@ static inline T Select(T val) { Instruction::Category InstCategory(const aarch64::InstData &inst) { switch (inst.iclass) { - case aarch64::InstName::INVALID: - return Instruction::kCategoryInvalid; + case aarch64::InstName::INVALID: return Instruction::kCategoryInvalid; // TODO(pag): B.cond. case aarch64::InstName::B: @@ -63,8 +61,7 @@ Instruction::Category InstCategory(const aarch64::InstData &inst) { return Instruction::kCategoryDirectJump; } - case aarch64::InstName::BR: - return Instruction::kCategoryIndirectJump; + case aarch64::InstName::BR: return Instruction::kCategoryIndirectJump; case aarch64::InstName::CBZ: case aarch64::InstName::CBNZ: @@ -72,42 +69,35 @@ Instruction::Category InstCategory(const aarch64::InstData &inst) { case aarch64::InstName::TBNZ: return Instruction::kCategoryConditionalBranch; - case aarch64::InstName::BL: - return Instruction::kCategoryDirectFunctionCall; + case aarch64::InstName::BL: return Instruction::kCategoryDirectFunctionCall; case aarch64::InstName::BLR: return Instruction::kCategoryIndirectFunctionCall; - case aarch64::InstName::RET: - return Instruction::kCategoryFunctionReturn; + case aarch64::InstName::RET: return Instruction::kCategoryFunctionReturn; - case aarch64::InstName::HLT: - return Instruction::kCategoryError; + case aarch64::InstName::HLT: return Instruction::kCategoryError; case aarch64::InstName::HVC: case aarch64::InstName::SMC: case aarch64::InstName::SVC: case aarch64::InstName::SYS: // Has aliases `IC`, `DC`, `AT`, and `TLBI`. - case aarch64::InstName::SYSL: - return Instruction::kCategoryAsyncHyperCall; + case aarch64::InstName::SYSL: return Instruction::kCategoryAsyncHyperCall; case aarch64::InstName::HINT: - case aarch64::InstName::NOP: - return Instruction::kCategoryNoOp; + case aarch64::InstName::NOP: return Instruction::kCategoryNoOp; // Note: These are implemented with synchronous hyper calls. - case aarch64::InstName::BRK: - return Instruction::kCategoryNormal; + case aarch64::InstName::BRK: return Instruction::kCategoryNormal; - default: - return Instruction::kCategoryNormal; + default: return Instruction::kCategoryNormal; } } class AArch64Arch final : public Arch { public: - AArch64Arch(llvm::LLVMContext *context_, - OSName os_name_, ArchName arch_name_); + AArch64Arch(llvm::LLVMContext *context_, OSName os_name_, + ArchName arch_name_); virtual ~AArch64Arch(void); @@ -118,9 +108,8 @@ class AArch64Arch final : public Arch { const char *ProgramCounterRegisterName(void) const final; // Decode an instruction. - bool DecodeInstruction( - uint64_t address, std::string_view instr_bytes, - Instruction &inst) const final; + bool DecodeInstruction(uint64_t address, std::string_view instr_bytes, + Instruction &inst) const final; // Maximum number of bytes in an instruction. uint64_t MaxInstructionSize(void) const final; @@ -135,8 +124,8 @@ class AArch64Arch final : public Arch { AArch64Arch(void) = delete; }; -AArch64Arch::AArch64Arch( - llvm::LLVMContext *context_, OSName os_name_, ArchName arch_name_) +AArch64Arch::AArch64Arch(llvm::LLVMContext *context_, OSName os_name_, + ArchName arch_name_) : Arch(context_, os_name_, arch_name_) {} AArch64Arch::~AArch64Arch(void) {} @@ -154,14 +143,11 @@ uint64_t AArch64Arch::MaxInstructionSize(void) const { llvm::Triple AArch64Arch::Triple(void) const { auto triple = BasicTriple(); switch (arch_name) { - case kArchAArch64LittleEndian: - triple.setArch(llvm::Triple::aarch64); - break; + case kArchAArch64LittleEndian: triple.setArch(llvm::Triple::aarch64); break; default: - LOG(FATAL) - << "Cannot get triple for non-AArch64 architecture " - << GetArchName(arch_name); + LOG(FATAL) << "Cannot get triple for non-AArch64 architecture " + << GetArchName(arch_name); break; } return triple; @@ -175,9 +161,8 @@ llvm::DataLayout AArch64Arch::DataLayout(void) const { break; default: - LOG(FATAL) - << "Cannot get data layout for non-AArch64 architecture " - << GetArchName(arch_name); + LOG(FATAL) << "Cannot get data layout for non-AArch64 architecture " + << GetArchName(arch_name); break; } return llvm::DataLayout(dl); @@ -199,17 +184,10 @@ enum RegUsage { kUseAsValue // Interpret X31 == XZR and W31 == WZR. }; -enum Action { - kActionRead, - kActionWrite, - kActionReadWrite -}; +enum Action { kActionRead, kActionWrite, kActionReadWrite }; // Immediate integer type. -enum ImmType { - kUnsigned, - kSigned -}; +enum ImmType { kUnsigned, kSigned }; // Note: Order is significant; extracted bits may be casted to this type. enum Extend : uint8_t { @@ -255,37 +233,26 @@ static Operand::ShiftRegister::Extend ShiftRegExtendType(Extend extend) { case kExtendUXTB: case kExtendUXTH: case kExtendUXTW: - case kExtendUXTX: - return Operand::ShiftRegister::kExtendUnsigned; + case kExtendUXTX: return Operand::ShiftRegister::kExtendUnsigned; case kExtendSXTB: case kExtendSXTH: case kExtendSXTW: - case kExtendSXTX: - return Operand::ShiftRegister::kExtendSigned; + case kExtendSXTX: return Operand::ShiftRegister::kExtendSigned; } return Operand::ShiftRegister::kExtendInvalid; } // Note: Order is significant; extracted bits may be casted to this type. -enum Shift : uint8_t { - kShiftLSL, - kShiftLSR, - kShiftASR, - kShiftROR -}; +enum Shift : uint8_t { kShiftLSL, kShiftLSR, kShiftASR, kShiftROR }; // Translate a shift encoding into an operand shift type used by the shift // register class. static Operand::ShiftRegister::Shift GetOperandShift(Shift s) { switch (s) { - case kShiftLSL: - return Operand::ShiftRegister::kShiftLeftWithZeroes; - case kShiftLSR: - return Operand::ShiftRegister::kShiftUnsignedRight; - case kShiftASR: - return Operand::ShiftRegister::kShiftSignedRight; - case kShiftROR: - return Operand::ShiftRegister::kShiftRightAround; + case kShiftLSL: return Operand::ShiftRegister::kShiftLeftWithZeroes; + case kShiftLSR: return Operand::ShiftRegister::kShiftUnsignedRight; + case kShiftASR: return Operand::ShiftRegister::kShiftSignedRight; + case kShiftROR: return Operand::ShiftRegister::kShiftRightAround; } return Operand::ShiftRegister::kShiftInvalid; } @@ -361,35 +328,26 @@ static std::string RegName(Action action, RegClass rclass, RegUsage rtype, aarch64::RegNum number) { switch (rclass) { case kRegX: - case kRegW: - return RegNameXW(action, rclass, rtype, number); + case kRegW: return RegNameXW(action, rclass, rtype, number); case kRegB: case kRegH: case kRegS: case kRegD: case kRegQ: - case kRegV: - return RegNameFP(action, rclass, rtype, number); + case kRegV: return RegNameFP(action, rclass, rtype, number); } } static uint64_t ReadRegSize(RegClass rclass) { switch (rclass) { - case kRegX: - return 64; - case kRegW: - return 32; - case kRegB: - return 8; - case kRegH: - return 16; - case kRegS: - return 32; - case kRegD: - return 64; + case kRegX: return 64; + case kRegW: return 32; + case kRegB: return 8; + case kRegH: return 16; + case kRegS: return 32; + case kRegD: return 64; case kRegQ: - case kRegV: - return 128; + case kRegV: return 128; } return 0; } @@ -397,15 +355,13 @@ static uint64_t ReadRegSize(RegClass rclass) { static uint64_t WriteRegSize(RegClass rclass) { switch (rclass) { case kRegX: - case kRegW: - return 64; + case kRegW: return 64; case kRegB: case kRegH: case kRegS: case kRegD: case kRegQ: - case kRegV: - return 128; + case kRegV: return 128; } return 0; } @@ -423,15 +379,13 @@ static Operand::Register Reg(Action action, RegClass rclass, RegUsage rtype, reg.name = RegName(action, rclass, rtype, reg_num); reg.size = ReadRegSize(rclass); } else { - LOG(FATAL) - << "Reg function only takes a simple read or write action."; + LOG(FATAL) << "Reg function only takes a simple read or write action."; } return reg; } -static void AddRegOperand(Instruction &inst, Action action, - RegClass rclass, RegUsage rtype, - aarch64::RegNum reg_num) { +static void AddRegOperand(Instruction &inst, Action action, RegClass rclass, + RegUsage rtype, aarch64::RegNum reg_num) { Operand op; op.type = Operand::kTypeRegister; @@ -452,8 +406,7 @@ static void AddRegOperand(Instruction &inst, Action action, static void AddShiftRegOperand(Instruction &inst, RegClass rclass, RegUsage rtype, aarch64::RegNum reg_num, - Shift shift_type, - uint64_t shift_size) { + Shift shift_type, uint64_t shift_size) { if (!shift_size) { AddRegOperand(inst, kActionRead, rclass, rtype, reg_num); } else { @@ -476,7 +429,7 @@ static void AddShiftRegOperand(Instruction &inst, RegClass rclass, static void AddExtendRegOperand(Instruction &inst, RegClass reg_class, RegUsage rtype, aarch64::RegNum reg_num, Extend extend_type, uint64_t output_size, - uint64_t shift_size=0) { + uint64_t shift_size = 0) { Operand op; op.shift_reg.reg = Reg(kActionRead, reg_class, rtype, reg_num); op.shift_reg.extend_op = ShiftRegExtendType(extend_type); @@ -506,8 +459,7 @@ static void AddExtendRegOperand(Instruction &inst, RegClass reg_class, } static void AddImmOperand(Instruction &inst, uint64_t val, - ImmType signedness=kUnsigned, - unsigned size=64) { + ImmType signedness = kUnsigned, unsigned size = 64) { Operand op; op.type = Operand::kTypeImmediate; op.action = Operand::kActionRead; @@ -549,7 +501,7 @@ static void AddPCRegMemOp(Instruction &inst, Action action, int64_t disp) { AddPCRegOp(inst, Operand::kActionWrite, disp, Operand::Address::kMemoryWrite); } else { - LOG(FATAL)<< __FUNCTION__ << " only accepts simple operand actions."; + LOG(FATAL) << __FUNCTION__ << " only accepts simple operand actions."; } } @@ -560,6 +512,7 @@ static void AddPCDisp(Instruction &inst, int64_t disp) { } static void AddNextPC(Instruction &inst) { + // add +4 as the PC displacement // emit an address computation operand AddPCDisp(inst, kInstructionSize); @@ -612,10 +565,10 @@ static constexpr auto kInvalidReg = static_cast(0xFF); // So we add in two operands: one that is a register write operand for Xn, // the other that is the value of (Xn + imm + imm). static void AddPreIndexMemOp(Instruction &inst, Action action, - uint64_t access_size, - aarch64::RegNum base_reg, uint64_t disp, - aarch64::RegNum dest_reg1=kInvalidReg, - aarch64::RegNum dest_reg2=kInvalidReg) { + uint64_t access_size, aarch64::RegNum base_reg, + uint64_t disp, + aarch64::RegNum dest_reg1 = kInvalidReg, + aarch64::RegNum dest_reg2 = kInvalidReg) { AddBasePlusOffsetMemOp(inst, action, access_size, base_reg, disp); auto addr_op = inst.operands[inst.operands.size() - 1]; @@ -656,10 +609,10 @@ static void AddPreIndexMemOp(Instruction &inst, Action action, // So we add in two operands: one that is a register write operand for Xn, // the other that is the value of (Xn + imm). static void AddPostIndexMemOp(Instruction &inst, Action action, - uint64_t access_size, - aarch64::RegNum base_reg, uint64_t disp, - aarch64::RegNum dest_reg1=kInvalidReg, - aarch64::RegNum dest_reg2=kInvalidReg) { + uint64_t access_size, aarch64::RegNum base_reg, + uint64_t disp, + aarch64::RegNum dest_reg1 = kInvalidReg, + aarch64::RegNum dest_reg2 = kInvalidReg) { AddBasePlusOffsetMemOp(inst, action, access_size, base_reg, 0); auto addr_op = inst.operands[inst.operands.size() - 1]; @@ -702,11 +655,10 @@ static void AddPostIndexMemOp(Instruction &inst, Action action, // So we add in two operands: one that is a register write operand for Xn, // the other that is the value of (Xn + imm). static void AddPostIndexMemOp(Instruction &inst, Action action, - uint64_t access_size, - aarch64::RegNum base_reg, + uint64_t access_size, aarch64::RegNum base_reg, aarch64::RegNum disp_reg, - aarch64::RegNum dest_reg1=kInvalidReg, - aarch64::RegNum dest_reg2=kInvalidReg) { + aarch64::RegNum dest_reg1 = kInvalidReg, + aarch64::RegNum dest_reg2 = kInvalidReg) { AddBasePlusOffsetMemOp(inst, action, access_size, base_reg, 0); auto addr_op = inst.operands[inst.operands.size() - 1]; @@ -739,7 +691,8 @@ static void AddPostIndexMemOp(Instruction &inst, Action action, static bool MostSignificantSetBit(uint64_t val, uint64_t *highest_out) { #if __has_builtin(__builtin_clzll) if (val) { - *highest_out = 63 - (__builtin_clzll(val) - (sizeof(unsigned long long) * 8 - 64)); + *highest_out = + 63 - (__builtin_clzll(val) - (sizeof(unsigned long long) * 8 - 64)); return true; } else { return false; @@ -811,11 +764,9 @@ static uint64_t Replicate(uint64_t val, uint64_t val_size, uint64_t goal_size) { // The gist of the format is that you hav static bool DecodeBitMasks(uint64_t N /* one bit */, uint64_t imms /* six bits */, - uint64_t immr /* six bits */, - bool is_immediate, - uint64_t data_size, - uint64_t *wmask_out=nullptr, - uint64_t *tmask_out=nullptr) { + uint64_t immr /* six bits */, bool is_immediate, + uint64_t data_size, uint64_t *wmask_out = nullptr, + uint64_t *tmask_out = nullptr) { uint64_t len = 0; if (!MostSignificantSetBit((N << 6ULL) | (~imms & 0x3fULL), &len)) { return false; @@ -841,8 +792,7 @@ static bool DecodeBitMasks(uint64_t N /* one bit */, const uint64_t d = diff & levels; // `diff`. const uint64_t welem = Ones(S + kOne); const uint64_t telem = Ones(d + kOne); - const uint64_t wmask = Replicate( - ROR(welem, esize, R), esize, data_size); + const uint64_t wmask = Replicate(ROR(welem, esize, R), esize, data_size); const uint64_t tmask = Replicate(telem, esize, data_size); if (wmask_out) { @@ -888,8 +838,9 @@ const char *AArch64Arch::ProgramCounterRegisterName(void) const { return "PC"; } -bool AArch64Arch::DecodeInstruction( - uint64_t address, std::string_view inst_bytes, Instruction &inst) const { +bool AArch64Arch::DecodeInstruction(uint64_t address, + std::string_view inst_bytes, + Instruction &inst) const { aarch64::InstData dinst = {}; auto bytes = reinterpret_cast(inst_bytes.data()); @@ -1076,6 +1027,7 @@ bool TryDecodeSTP_Q_LDSTPAIR_OFF(const InstData &data, Instruction &inst) { // LDP , , [], # bool TryDecodeLDP_32_LDSTPAIR_POST(const InstData &data, Instruction &inst) { + // `if L:opc<0> == '01' || opc == '11' then UnallocatedEncoding();`. if ((!data.L && (data.opc & 1)) || data.opc == 3) { return false; @@ -1092,6 +1044,7 @@ bool TryDecodeLDP_32_LDSTPAIR_POST(const InstData &data, Instruction &inst) { // LDP , , [], # bool TryDecodeLDP_64_LDSTPAIR_POST(const InstData &data, Instruction &inst) { + // `if L:opc<0> == '01' || opc == '11' then UnallocatedEncoding();`. if ((!data.L && (data.opc & 1)) || data.opc == 3) { return false; @@ -1138,13 +1091,14 @@ bool TryDecodeLDPSW_64_LDSTPAIR_PRE(const InstData &data, Instruction &inst) { AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rt); AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rt2); AddPreIndexMemOp(inst, kActionRead, 64, data.Rn, - static_cast(data.imm7.simm7) << 2, - data.Rt, data.Rt2); + static_cast(data.imm7.simm7) << 2, data.Rt, + data.Rt2); return true; } // LDP , , [, #]! bool TryDecodeLDP_32_LDSTPAIR_PRE(const InstData &data, Instruction &inst) { + // `if L:opc<0> == '01' || opc == '11' then UnallocatedEncoding();`. if ((!data.L && (data.opc & 1)) || data.opc == 3) { return false; @@ -1155,13 +1109,14 @@ bool TryDecodeLDP_32_LDSTPAIR_PRE(const InstData &data, Instruction &inst) { AddRegOperand(inst, kActionWrite, kRegW, kUseAsValue, data.Rt); AddRegOperand(inst, kActionWrite, kRegW, kUseAsValue, data.Rt2); AddPreIndexMemOp(inst, kActionRead, 64, data.Rn, - static_cast(data.imm7.simm7) << 2, - data.Rt, data.Rt2); + static_cast(data.imm7.simm7) << 2, data.Rt, + data.Rt2); return true; } // LDP , , [, #]! bool TryDecodeLDP_64_LDSTPAIR_PRE(const InstData &data, Instruction &inst) { + // `if L:opc<0> == '01' || opc == '11' then UnallocatedEncoding();`. if ((!data.L && (data.opc & 1)) || data.opc == 3) { return false; @@ -1172,13 +1127,14 @@ bool TryDecodeLDP_64_LDSTPAIR_PRE(const InstData &data, Instruction &inst) { AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rt); AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rt2); AddPreIndexMemOp(inst, kActionRead, 128, data.Rn, - static_cast(data.imm7.simm7) << 3, - data.Rt, data.Rt2); + static_cast(data.imm7.simm7) << 3, data.Rt, + data.Rt2); return true; } // LDP , , [{, #}] bool TryDecodeLDP_32_LDSTPAIR_OFF(const InstData &data, Instruction &inst) { + // `if L:opc<0> == '01' || opc == '11' then UnallocatedEncoding();`. if ((!data.L && (data.opc & 1)) || data.opc == 3) { return false; @@ -1195,6 +1151,7 @@ bool TryDecodeLDP_32_LDSTPAIR_OFF(const InstData &data, Instruction &inst) { // LDP , , [{, #}] bool TryDecodeLDP_64_LDSTPAIR_OFF(const InstData &data, Instruction &inst) { + // `if L:opc<0> == '01' || opc == '11' then UnallocatedEncoding();`. if ((!data.L && (data.opc & 1)) || data.opc == 3) { return false; @@ -1244,16 +1201,14 @@ bool TryDecodeLDR_64_LDST_IMMPRE(const InstData &data, Instruction &inst) { // LDR , [{, #}] bool TryDecodeLDR_32_LDST_POS(const InstData &data, Instruction &inst) { AddRegOperand(inst, kActionWrite, kRegW, kUseAsValue, data.Rt); - AddBasePlusOffsetMemOp(inst, kActionRead, 32, data.Rn, - data.imm12.uimm << 2); + AddBasePlusOffsetMemOp(inst, kActionRead, 32, data.Rn, data.imm12.uimm << 2); return true; } // LDR , [{, #}] bool TryDecodeLDR_64_LDST_POS(const InstData &data, Instruction &inst) { AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rt); - AddBasePlusOffsetMemOp(inst, kActionRead, 64, data.Rn, - data.imm12.uimm << 3); + AddBasePlusOffsetMemOp(inst, kActionRead, 64, data.Rn, data.imm12.uimm << 3); return true; } @@ -1273,8 +1228,8 @@ bool TryDecodeLDR_64_LOADLIT(const InstData &data, Instruction &inst) { return true; } -static bool TryDecodeLDR_n_LDST_REGOFF( - const InstData &data, Instruction &inst, RegClass val_class) { +static bool TryDecodeLDR_n_LDST_REGOFF(const InstData &data, Instruction &inst, + RegClass val_class) { if (!(data.option & 2)) { // Sub word indexing. return false; // `if option<1> == '0' then UnallocatedEncoding();`. } @@ -1284,8 +1239,8 @@ static bool TryDecodeLDR_n_LDST_REGOFF( auto rclass = ExtendTypeToRegClass(extend_type); AddRegOperand(inst, kActionWrite, val_class, kUseAsValue, data.Rt); AddBasePlusOffsetMemOp(inst, kActionRead, 8U << scale, data.Rn, 0); - AddExtendRegOperand(inst, rclass, kUseAsValue, data.Rm, extend_type, - 64, shift); + AddExtendRegOperand(inst, rclass, kUseAsValue, data.Rm, extend_type, 64, + shift); return true; } @@ -1347,8 +1302,8 @@ bool TryDecodeSTR_64_LDST_POS(const InstData &data, Instruction &inst) { return true; } -static bool TryDecodeSTR_n_LDST_REGOFF( - const InstData &data, Instruction &inst, RegClass val_class) { +static bool TryDecodeSTR_n_LDST_REGOFF(const InstData &data, Instruction &inst, + RegClass val_class) { if (!(data.option & 2)) { // Sub word indexing. return false; // `if option<1> == '0' then UnallocatedEncoding();`. } @@ -1357,8 +1312,8 @@ static bool TryDecodeSTR_n_LDST_REGOFF( auto shift = data.S ? scale : 0U; AddRegOperand(inst, kActionRead, val_class, kUseAsValue, data.Rt); AddBasePlusOffsetMemOp(inst, kActionWrite, 8U << data.size, data.Rn, 0); - AddExtendRegOperand(inst, ExtendTypeToRegClass(extend_type), - kUseAsValue, data.Rm, extend_type, 64, shift); + AddExtendRegOperand(inst, ExtendTypeToRegClass(extend_type), kUseAsValue, + data.Rm, extend_type, 64, shift); return true; } @@ -1450,8 +1405,8 @@ bool TryDecodeADRP_ONLY_PCRELADDR(const InstData &data, Instruction &inst) { // B