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Commit 4d87b87

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agustinovagustinov
committed
Add some cedrus regs
1 parent 985e914 commit 4d87b87

3 files changed

Lines changed: 62 additions & 28 deletions

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‎cedrus.c‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ static struct cedrus
4747
pthread_mutex_t device_lock;
4848
} ve = { .fd = -1, .device_lock = PTHREAD_MUTEX_INITIALIZER };
4949

50-
EXPORT struct cedrus *cedrus_open(void)
50+
EXPORT cedrus_t *cedrus_open(void)
5151
{
5252
pthread_mutex_lock(&open_lock);
5353
if (ve.fd != -1) {
@@ -96,14 +96,16 @@ EXPORT struct cedrus *cedrus_open(void)
9696
ioctl(ve.fd, IOCTL_SET_VE_FREQ + ve.ioctl_offset, 320);
9797
ioctl(ve.fd, IOCTL_RESET_VE + ve.ioctl_offset, 0);
9898

99-
writel(0x00130007, ve.regs + VE_CTRL);
99+
writel(0x00130000 | VE_CTRL_ENGINE_RESET, ve.regs + VE_CTRL);
100100

101+
//printf("[libcedrus SUNXI] VE version 0x%04x opened\n", ve.version);
101102
open_count++;
102103
pthread_mutex_unlock(&open_lock);
103104
return &ve;
104105

105106
unmap:
106107
munmap(ve.regs, 0x800);
108+
107109
close:
108110
close(ve.fd);
109111
ve.fd = -1;
@@ -152,11 +154,11 @@ EXPORT int cedrus_ve_wait(struct cedrus *dev, int timeout)
152154
if (!dev)
153155
return -1;
154156

155-
if (((reg = readl(dev->regs + VE_CTRL)) & CEDRUS_ENGINE_H264_ENC) == CEDRUS_ENGINE_H264_ENC) {
157+
if (((reg = readl(dev->regs + VE_CTRL)) & VE_CTRL_ENGINE_FIELD) == VE_CTRL_ENGINE_AVC) {
156158
engine_wait = IOCTL_WAIT_VE_DE + dev->ioctl_offset;
157159
}
158160

159-
//printf("we engine %04X, we wait %d\n", reg, engine_wait);
161+
//printf("ve engine %04X, ve wait %d\n", reg, engine_wait);
160162

161163
return ioctl(dev->fd, engine_wait, timeout);
162164
}
@@ -166,7 +168,7 @@ EXPORT void *cedrus_ve_get(struct cedrus *dev, enum cedrus_engine engine, uint32
166168
if (!dev || pthread_mutex_lock(&dev->device_lock))
167169
return NULL;
168170

169-
writel(0x00130000 | (engine & 0xf) | (flags & ~0xf), dev->regs + VE_CTRL);
171+
writel(0x00130000 | (engine & VE_CTRL_ENGINE_FIELD) | (flags & ~VE_CTRL_ENGINE_FIELD), dev->regs + VE_CTRL);
170172

171173
return dev->regs;
172174
}
@@ -176,7 +178,7 @@ EXPORT void cedrus_ve_put(struct cedrus *dev)
176178
if (!dev)
177179
return;
178180

179-
writel(0x00130007, dev->regs + VE_CTRL);
181+
writel(0x00130000 | VE_CTRL_ENGINE_RESET, dev->regs + VE_CTRL);
180182
pthread_mutex_unlock(&dev->device_lock);
181183
}
182184

‎cedrus.h‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,10 +22,16 @@
2222

2323
#include <stddef.h>
2424
#include <stdint.h>
25+
#include "cedrus_regs.h"
2526

2627
typedef struct cedrus cedrus_t;
2728

28-
enum cedrus_engine { CEDRUS_ENGINE_MPEG = 0x0, CEDRUS_ENGINE_H264 = 0x1, CEDRUS_ENGINE_HEVC = 0x4, CEDRUS_ENGINE_H264_ENC = 0xb };
29+
enum cedrus_engine {
30+
CEDRUS_ENGINE_MPEG = VE_CTRL_ENGINE_MPEG,
31+
CEDRUS_ENGINE_H264 = VE_CTRL_ENGINE_H264,
32+
CEDRUS_ENGINE_HEVC = VE_CTRL_ENGINE_HEVC,
33+
CEDRUS_ENGINE_AVC = VE_CTRL_ENGINE_AVC
34+
};
2935

3036
cedrus_t *cedrus_open(void);
3137
void cedrus_close(cedrus_t *dev);

‎cedrus_regs.h‎

Lines changed: 47 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ static inline uint32_t readl(void *addr)
3232
return *((volatile uint32_t *) addr);
3333
}
3434

35+
// VE general registers
3536
#define VE_CTRL 0x000
3637
#define VE_RESET 0x004
3738
#define VE_OUTPUT_CHROMA_OFFSET 0x0c4
@@ -40,6 +41,25 @@ static inline uint32_t readl(void *addr)
4041
#define VE_OUTPUT_FORMAT 0x0ec
4142
#define VE_VERSION 0x0f0
4243

44+
// VE_CTRL register values
45+
#define VE_CTRL_ENGINE_MPEG 0x00
46+
#define VE_CTRL_ENGINE_H264 0x01
47+
#define VE_CTRL_ENGINE_HEVC 0x04
48+
#define VE_CTRL_ENGINE_RESET 0x07
49+
#define VE_CTRL_ENGINE_AVC 0x0b
50+
#define VE_CTRL_ENGINE_FIELD 0x0f
51+
#define VE_CTRL_ENABLE_ISP 0x40
52+
#define VE_CTRL_ENABLE_AVC 0x80
53+
54+
// VE_OUTPUT_FORMAT register values
55+
#define VE_OUTPUT_FORMAT_TILE32x32 0x00
56+
#define VE_OUTPUT_FORMAT_TILE128x32 0x10
57+
#define VE_OUTPUT_FORMAT_I420 0x20
58+
#define VE_OUTPUT_FORMAT_YV12 0x30
59+
#define VE_OUTPUT_FORMAT_NV12 0x40
60+
#define VE_OUTPUT_FORMAT_NV21 0x50
61+
62+
// VE MPEG engine registers
4363
#define VE_MPEG_PIC_HDR 0x100
4464
#define VE_MPEG_VOP_HDR 0x104
4565
#define VE_MPEG_SIZE 0x108
@@ -65,17 +85,15 @@ static inline uint32_t readl(void *addr)
6585
#define VE_MPEG_BACK_CHROMA 0x15c
6686
#define VE_MPEG_IQ_MIN_INPUT 0x180
6787
#define VE_MPEG_QP_INPUT 0x184
68-
6988
#define VE_MPEG_JPEG_SIZE 0x1b8
7089
#define VE_MPEG_JPEG_RES_INT 0x1c0
71-
7290
#define VE_MPEG_ROT_LUMA 0x1cc
7391
#define VE_MPEG_ROT_CHROMA 0x1d0
7492
#define VE_MPEG_SDROT_CTRL 0x1d4
93+
#define VE_MPEG_SRAM_ADDR 0x1e0
94+
#define VE_MPEG_SRAM_DATA 0x1e4
7595

76-
#define VE_MPEG_RAM_WRITE_PTR 0x1e0
77-
#define VE_MPEG_RAM_WRITE_DATA 0x1e4
78-
96+
// VE H264 engine registers
7997
#define VE_H264_FRAME_SIZE 0x200
8098
#define VE_H264_PIC_HDR 0x204
8199
#define VE_H264_SLICE_HDR 0x208
@@ -99,15 +117,17 @@ static inline uint32_t readl(void *addr)
99117
#define VE_H264_MB_ADDR 0x260
100118
#define VE_H264_ERROR 0x2b8
101119
#define VE_H264_BASIC_BITS 0x2dc
102-
#define VE_H264_RAM_WRITE_PTR 0x2e0
103-
#define VE_H264_RAM_WRITE_DATA 0x2e4
120+
#define VE_H264_SRAM_ADDR 0x2e0
121+
#define VE_H264_SRAM_DATA 0x2e4
104122

105-
#define VE_SRAM_H264_PRED_WEIGHT_TABLE 0x000
106-
#define VE_SRAM_H264_FRAMEBUFFER_LIST 0x400
107-
#define VE_SRAM_H264_REF_LIST0 0x640
108-
#define VE_SRAM_H264_REF_LIST1 0x664
109-
#define VE_SRAM_H264_SCALING_LISTS 0x800
123+
// VE_H264_SRAM_ADDR register values
124+
#define VE_H264_SRAM_PRED_WEIGHT_TABLE 0x000
125+
#define VE_H264_SRAM_FRAMEBUFFER_LIST 0x400
126+
#define VE_H264_SRAM_REF_LIST0 0x640
127+
#define VE_H264_SRAM_REF_LIST1 0x664
128+
#define VE_H264_SRAM_SCALING_LISTS 0x800
110129

130+
// VE HEVC engine registers
111131
#define VE_HEVC_NAL_HDR 0x500
112132
#define VE_HEVC_SPS 0x504
113133
#define VE_HEVC_PIC_SIZE 0x508
@@ -138,30 +158,36 @@ static inline uint32_t readl(void *addr)
138158
#define VE_HEVC_SRAM_ADDR 0x5e0
139159
#define VE_HEVC_SRAM_DATA 0x5e4
140160

141-
#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L0 0x000
142-
#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L0 0x020
143-
#define VE_SRAM_HEVC_PRED_WEIGHT_LUMA_L1 0x060
144-
#define VE_SRAM_HEVC_PRED_WEIGHT_CHROMA_L1 0x080
145-
#define VE_SRAM_HEVC_PIC_LIST 0x400
146-
#define VE_SRAM_HEVC_SCALING_LISTS 0x800
147-
#define VE_SRAM_HEVC_REF_PIC_LIST0 0xc00
148-
#define VE_SRAM_HEVC_REF_PIC_LIST1 0xc10
149-
161+
// VE_HEVC_SRAM_ADDR register values
162+
#define VE_HEVC_SRAM_PRED_WEIGHT_LUMA_L0 0x000
163+
#define VE_HEVC_SRAM_PRED_WEIGHT_CHROMA_L0 0x020
164+
#define VE_HEVC_SRAM_PRED_WEIGHT_LUMA_L1 0x060
165+
#define VE_HEVC_SRAM_PRED_WEIGHT_CHROMA_L1 0x080
166+
#define VE_HEVC_SRAM_PIC_LIST 0x400
167+
#define VE_HEVC_SRAM_SCALING_LISTS 0x800
168+
#define VE_HEVC_SRAM_REF_PIC_LIST0 0xc00
169+
#define VE_HEVC_SRAM_REF_PIC_LIST1 0xc10
170+
171+
// VE ISP engine registers
150172
#define VE_ISP_INPUT_SIZE 0xa00
151173
#define VE_ISP_INPUT_STRIDE 0xa04
174+
#define VE_ISP_CTRL 0xa08
152175
#define VE_ISP_INPUT_LUMA 0xa78
153176
#define VE_ISP_INPUT_CHROMA 0xa7c
154177

178+
// VE AVC engine registers
155179
#define VE_AVC_PARAM 0xb04
156180
#define VE_AVC_QP 0xb08
157181
#define VE_AVC_MOTION_EST 0xb10
158182
#define VE_AVC_CTRL 0xb14
159183
#define VE_AVC_TRIGGER 0xb18
160184
#define VE_AVC_STATUS 0xb1c
161185
#define VE_AVC_BASIC_BITS 0xb20
186+
#define VE_AVC_UNK_BUF 0xb60
162187
#define VE_AVC_VLE_ADDR 0xb80
163188
#define VE_AVC_VLE_END 0xb84
164189
#define VE_AVC_VLE_OFFSET 0xb88
190+
#define VE_AVC_VLE_MAX 0xb8c
165191
#define VE_AVC_VLE_LENGTH 0xb90
166192
#define VE_AVC_REF_LUMA 0xba0
167193
#define VE_AVC_REF_CHROMA 0xba4

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