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The newer BROM FEL path copies received USB data byte-by-byte from the
MUSB FIFO. Even after switching the controller to high-speed mode, this
leaves large post-SPL DRAM writes far slower than the USB link can
support.
After SPL has initialized DRAM, install a parameterized RX DMA thunk for
writes into the known DRAM window. The thunk builds the MMU remap it
needs, hooks the BROM RX FIFO copy helper, and replaces it with a
MUSB/USBC endpoint-DMA receive path. It routes the active RX endpoint
DRQ through VEND0 before starting the internal DMA channel, so the FEL
wire protocol stays unchanged.
Put the common thunk code in fel_lib.c and install it from the shared
aw_fel_write_buffer() path. This makes normal writes and FIT image
loading use the same post-SPL DRAM write preparation path. Put the
SoC-specific hook, translation-table and shadow-page addresses in the
SoC table. Enable the path for SoCs whose BROM dumps contain the same
FIFO-copy helper ABI and compatible MUSB register layout: A33, A64, H3,
H5, A63, H6, H616, V853, R528/T113-S3/T528, V5, A523 and A133.
Coalesce full high-speed packets into bounded RX DMA requests. Keep each
host write as a single AW_FEL_1_WRITE request, and have the thunk copy
the final short packet with PIO after stopping DMA. This keeps arbitrary
post-SPL DRAM write sizes working without changing the FEL wire protocol.
Use a 192 KiB DMA request cap on most supported SoCs; 256 KiB requests
can time out while the host is writing. The R528/T113-S3/T528 path uses
a smaller 16 KiB cap based on tested hardware behavior.
Add the checked-in DMA thunk header to the sunxi-fel prerequisites and
thunk documentation. This makes the binary rebuild when the generated
header changes without making the sunxi-fel target regenerate thunk
headers.
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
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