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fel: soc_info: add GPIO and CCU base address
Some sunxi-fel features like the SPI flash access need to program the GPIO/pinctrl and clock controllers, located at different MMIO base addresses across all the various SoC generations. Add a GPIO and clock controller base address to our soc_info struct, and add the respective base addresses for each supported SoC to the SoC table. Also add flags to mark the generation of each IP: the D1 pinctrl change (each GPIO port uses 48 bytes instead of 36), and the H6 clock change (moving clock gates and resets into per-peripheral registers). This is not used at the moment, but will be soon. Signed-off-by: Andre Przywara <osp@andrep.de>
1 parent 37ef96e commit 7f501f3

2 files changed

Lines changed: 80 additions & 3 deletions

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‎soc_info.c‎

Lines changed: 64 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -334,6 +334,8 @@ soc_info_t soc_info_table[] = {
334334
.sram_size = 48 * 1024,
335335
.sid_base = 0x01C23800,
336336
.watchdog = &wd_a10_compat,
337+
.gpio_base = SUNXI_PIO_BASE,
338+
.ccu_base = AW_CCM_BASE,
337339
.flags = NEEDS_L2EN,
338340
},{
339341
.soc_id = 0x1625, /* Allwinner A10s, A13, R8 */
@@ -344,6 +346,8 @@ soc_info_t soc_info_table[] = {
344346
.sram_size = 48 * 1024,
345347
.sid_base = 0x01C23800,
346348
.watchdog = &wd_a10_compat,
349+
.gpio_base = SUNXI_PIO_BASE,
350+
.ccu_base = AW_CCM_BASE,
347351
.flags = NEEDS_L2EN,
348352
},{
349353
.soc_id = 0x1651, /* Allwinner A20 */
@@ -355,6 +359,8 @@ soc_info_t soc_info_table[] = {
355359
.sid_base = 0x01C23800,
356360
.sid_sections = generic_2k_sid_maps,
357361
.watchdog = &wd_a10_compat,
362+
.gpio_base = SUNXI_PIO_BASE,
363+
.ccu_base = AW_CCM_BASE,
358364
},{
359365
.soc_id = 0x1650, /* Allwinner A23 */
360366
.name = "A23",
@@ -365,6 +371,8 @@ soc_info_t soc_info_table[] = {
365371
.sid_base = 0x01C23800,
366372
.sid_sections = generic_2k_sid_maps,
367373
.watchdog = &wd_h3_compat,
374+
.gpio_base = SUNXI_PIO_BASE,
375+
.ccu_base = AW_CCM_BASE,
368376
},{
369377
.soc_id = 0x1633, /* Allwinner A31 */
370378
.name = "A31",
@@ -373,6 +381,8 @@ soc_info_t soc_info_table[] = {
373381
.swap_buffers = a31_sram_swap_buffers,
374382
.sram_size = 32 * 1024,
375383
.watchdog = &wd_h3_compat,
384+
.gpio_base = SUNXI_PIO_BASE,
385+
.ccu_base = AW_CCM_BASE,
376386
},{
377387
.soc_id = 0x1667, /* Allwinner A33, R16 */
378388
.name = "A33",
@@ -383,6 +393,8 @@ soc_info_t soc_info_table[] = {
383393
.sid_base = 0x01C23800,
384394
.sid_sections = generic_2k_sid_maps,
385395
.watchdog = &wd_h3_compat,
396+
.gpio_base = SUNXI_PIO_BASE,
397+
.ccu_base = AW_CCM_BASE,
386398
},{
387399
.soc_id = 0x1689, /* Allwinner A64 */
388400
.name = "A64",
@@ -398,6 +410,8 @@ soc_info_t soc_info_table[] = {
398410
/* Check L.NOP in the OpenRISC reset vector */
399411
.needs_smc_workaround_if_zero_word_at_addr = 0x40004,
400412
.watchdog = &wd_h3_compat,
413+
.gpio_base = SUNXI_PIO_BASE,
414+
.ccu_base = AW_CCM_BASE,
401415
},{
402416
.soc_id = 0x1639, /* Allwinner A80 */
403417
.name = "A80",
@@ -410,6 +424,8 @@ soc_info_t soc_info_table[] = {
410424
.sid_offset = 0x200,
411425
.sid_sections = generic_2k_sid_maps,
412426
.watchdog = &wd_a80,
427+
.gpio_base = A80_PIO_BASE,
428+
.ccu_base = A80_CCM_BASE,
413429
},{
414430
.soc_id = 0x1663, /* Allwinner F1C100s (all new sun3i?) */
415431
.name = "F1C100s",
@@ -419,6 +435,8 @@ soc_info_t soc_info_table[] = {
419435
.sram_size = 32 * 1024,
420436
/* No SID */
421437
.watchdog = &wd_h3_compat,
438+
.gpio_base = SUNXI_PIO_BASE,
439+
.ccu_base = AW_CCM_BASE,
422440
},{
423441
.soc_id = 0x1673, /* Allwinner A83T */
424442
.name = "A83T",
@@ -431,6 +449,8 @@ soc_info_t soc_info_table[] = {
431449
.sid_offset = 0x200,
432450
.sid_sections = generic_2k_sid_maps,
433451
.watchdog = &wd_h3_compat,
452+
.gpio_base = SUNXI_PIO_BASE,
453+
.ccu_base = AW_CCM_BASE,
434454
},{
435455
.soc_id = 0x1680, /* Allwinner H3, H2+ */
436456
.name = "H3",
@@ -445,6 +465,8 @@ soc_info_t soc_info_table[] = {
445465
/* Check L.NOP in the OpenRISC reset vector */
446466
.needs_smc_workaround_if_zero_word_at_addr = 0x40004,
447467
.watchdog = &wd_h3_compat,
468+
.gpio_base = SUNXI_PIO_BASE,
469+
.ccu_base = AW_CCM_BASE,
448470
.flags = NEEDS_SID_FIX,
449471
},{
450472
.soc_id = 0x1681, /* Allwinner V3s */
@@ -457,6 +479,8 @@ soc_info_t soc_info_table[] = {
457479
.sid_base = 0x01C23800,
458480
.sid_sections = generic_2k_sid_maps,
459481
.watchdog = &wd_h3_compat,
482+
.gpio_base = SUNXI_PIO_BASE,
483+
.ccu_base = AW_CCM_BASE,
460484
},{
461485
.soc_id = 0x1708, /* Allwinner T7 */
462486
.name = "T7",
@@ -469,6 +493,9 @@ soc_info_t soc_info_table[] = {
469493
.sid_offset = 0x200,
470494
.sid_sections = t7_sid_maps,
471495
.watchdog = &wd_h6_compat,
496+
.gpio_base = H6_PIO_BASE,
497+
.ccu_base = H6_CCM_BASE,
498+
.flags = H6_STYLE_CLOCKS,
472499
},{
473500
.soc_id = 0x1718, /* Allwinner H5 */
474501
.name = "H5",
@@ -484,6 +511,8 @@ soc_info_t soc_info_table[] = {
484511
/* Check L.NOP in the OpenRISC reset vector */
485512
.needs_smc_workaround_if_zero_word_at_addr = 0x40004,
486513
.watchdog = &wd_h3_compat,
514+
.gpio_base = SUNXI_PIO_BASE,
515+
.ccu_base = AW_CCM_BASE,
487516
},{
488517
.soc_id = 0x1701, /* Allwinner R40 */
489518
.name = "R40",
@@ -495,6 +524,8 @@ soc_info_t soc_info_table[] = {
495524
.sid_offset = 0x200,
496525
.sid_sections = r40_sid_maps,
497526
.watchdog = &wd_a10_compat,
527+
.gpio_base = SUNXI_PIO_BASE,
528+
.ccu_base = AW_CCM_BASE,
498529
},{
499530
.soc_id = 0x1719, /* Allwinner A63 */
500531
.name = "A63",
@@ -508,6 +539,9 @@ soc_info_t soc_info_table[] = {
508539
.sid_sections = generic_2k_sid_maps,
509540
.rvbar_reg = 0x09010040,
510541
.watchdog = &wd_h6_compat,
542+
.gpio_base = H6_PIO_BASE,
543+
.ccu_base = H6_CCM_BASE,
544+
.flags = H6_STYLE_CLOCKS,
511545
},{
512546
.soc_id = 0x1728, /* Allwinner H6 */
513547
.name = "H6",
@@ -523,6 +557,9 @@ soc_info_t soc_info_table[] = {
523557
/* Check L.NOP in the OpenRISC reset vector */
524558
.needs_smc_workaround_if_zero_word_at_addr = 0x100004,
525559
.watchdog = &wd_h6_compat,
560+
.gpio_base = H6_PIO_BASE,
561+
.ccu_base = H6_CCM_BASE,
562+
.flags = H6_STYLE_CLOCKS,
526563
},{
527564
.soc_id = 0x1816, /* Allwinner V536 */
528565
.name = "V536",
@@ -535,6 +572,9 @@ soc_info_t soc_info_table[] = {
535572
.sid_offset = 0x200,
536573
.sid_sections = generic_2k_sid_maps,
537574
.watchdog = &wd_h6_compat,
575+
.gpio_base = H6_PIO_BASE,
576+
.ccu_base = H6_CCM_BASE,
577+
.flags = H6_STYLE_CLOCKS,
538578
},{
539579
.soc_id = 0x1817, /* Allwinner V831 */
540580
.name = "V831",
@@ -547,6 +587,9 @@ soc_info_t soc_info_table[] = {
547587
.sid_offset = 0x200,
548588
.sid_sections = generic_2k_sid_maps,
549589
.watchdog = &wd_h6_compat,
590+
.gpio_base = H6_PIO_BASE,
591+
.ccu_base = H6_CCM_BASE,
592+
.flags = H6_STYLE_CLOCKS,
550593
},{
551594
.soc_id = 0x1823, /* Allwinner H616 */
552595
.name = "H616",
@@ -562,6 +605,9 @@ soc_info_t soc_info_table[] = {
562605
.rvbar_reg_alt= 0x08100040,
563606
.ver_reg = 0x03000024,
564607
.watchdog = &wd_h6_compat,
608+
.gpio_base = H6_PIO_BASE,
609+
.ccu_base = H6_CCM_BASE,
610+
.flags = H6_STYLE_CLOCKS,
565611
},{
566612
.soc_id = 0x1851, /* Allwinner R329 */
567613
.name = "R329",
@@ -576,6 +622,9 @@ soc_info_t soc_info_table[] = {
576622
.sid_sections = generic_2k_sid_maps,
577623
.rvbar_reg = 0x08100040,
578624
.watchdog = &wd_h6_compat,
625+
.gpio_base = R329_PIO_BASE,
626+
.ccu_base = R329_CCM_BASE,
627+
.flags = FLAGS_NCAT2,
579628
},{
580629
.soc_id = 0x1886, /* Allwinner V853 */
581630
.name = "V853",
@@ -588,7 +637,9 @@ soc_info_t soc_info_table[] = {
588637
.sid_offset = 0x200,
589638
.sid_sections = generic_2k_sid_maps,
590639
.watchdog = &wd_v853_compat,
591-
.flags = NEEDS_ICACHE_FIX,
640+
.gpio_base = V853_PIO_BASE,
641+
.ccu_base = R329_CCM_BASE,
642+
.flags = NEEDS_ICACHE_FIX | FLAGS_NCAT2,
592643
},{
593644
.soc_id = 0x1859, /* Allwinner D1/D1s/R528/T113-S3 */
594645
.name = "R528",
@@ -601,7 +652,9 @@ soc_info_t soc_info_table[] = {
601652
.sid_offset = 0x200,
602653
.sid_sections = generic_2k_sid_maps,
603654
.watchdog = &wd_v853_compat,
604-
.flags = NEEDS_ICACHE_FIX,
655+
.gpio_base = V853_PIO_BASE,
656+
.ccu_base = R329_CCM_BASE,
657+
.flags = NEEDS_ICACHE_FIX | FLAGS_NCAT2,
605658
},{
606659
.soc_id = 0x1721, /* Allwinner V5 */
607660
.name = "V5",
@@ -614,6 +667,9 @@ soc_info_t soc_info_table[] = {
614667
.sid_offset = 0x200,
615668
.sid_sections = generic_2k_sid_maps,
616669
.watchdog = &wd_h6_compat,
670+
.gpio_base = H6_PIO_BASE,
671+
.ccu_base = H6_CCM_BASE,
672+
.flags = H6_STYLE_CLOCKS,
617673
},{
618674
.soc_id = 0x1890, /* Allwinner A523 */
619675
.name = "A523",
@@ -627,7 +683,9 @@ soc_info_t soc_info_table[] = {
627683
.sid_sections = generic_2k_sid_maps,
628684
.rvbar_reg = 0x08000040,
629685
.watchdog = &wd_a523_compat,
630-
.flags = NEEDS_ICACHE_FIX,
686+
.gpio_base = V853_PIO_BASE,
687+
.ccu_base = R329_CCM_BASE,
688+
.flags = NEEDS_ICACHE_FIX | FLAGS_NCAT2,
631689
},{
632690
.soc_id = 0x1855, /* Allwinner A133 */
633691
.name = "A133",
@@ -642,6 +700,9 @@ soc_info_t soc_info_table[] = {
642700
.rvbar_reg = 0x08100040,
643701
.needs_smc_workaround_if_zero_word_at_addr = 0x100004,
644702
.watchdog = &wd_h6_compat,
703+
.gpio_base = H6_PIO_BASE,
704+
.ccu_base = H6_CCM_BASE,
705+
.flags = H6_STYLE_CLOCKS,
645706
},{
646707
.swap_buffers = NULL /* End of the table */
647708
}

‎soc_info.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,8 +82,22 @@ enum soc_flags {
8282
NEEDS_L2EN = BIT(0),
8383
NEEDS_SID_FIX = BIT(1),
8484
NEEDS_ICACHE_FIX = BIT(2),
85+
H6_STYLE_CLOCKS = BIT(3),
86+
GPIO_NCAT2 = BIT(4),
8587
};
8688

89+
#define FLAGS_NCAT2 (GPIO_NCAT2 | H6_STYLE_CLOCKS)
90+
91+
#define AW_CCM_BASE 0x01c20000
92+
#define SUNXI_PIO_BASE 0x01c20800
93+
#define A80_CCM_BASE 0x06000000
94+
#define A80_PIO_BASE 0x06000800
95+
#define H6_PIO_BASE 0x0300b000
96+
#define H6_CCM_BASE 0x03001000
97+
#define V853_PIO_BASE 0x02000000
98+
#define R329_PIO_BASE 0x02000400
99+
#define R329_CCM_BASE 0x02001000
100+
87101
/*
88102
* Each SoC variant may have its own list of memory buffers to be exchanged
89103
* and the information about the placement of the thunk code, which handles
@@ -142,6 +156,8 @@ typedef struct {
142156
uint32_t needs_smc_workaround_if_zero_word_at_addr;
143157
uint32_t sram_size; /* Usable contiguous SRAM at spl_addr */
144158
sram_swap_buffers *swap_buffers;
159+
uint32_t gpio_base;
160+
uint32_t ccu_base;
145161
uint32_t flags;
146162
} soc_info_t;
147163

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