spi: move SPI0 base address into soc_info

Use the main soc table to also store the first SPI controller's MMIO
base address, so that we don't need to decide this in the SPI flash
code.
Only SoCs that are covered by fel-spiflash.c get a base address assigned,
so this value being not 0 is used as an indicator that the SoC is
supported.

This will simplify supporting future generations of SoCs.

Signed-off-by: Andre Przywara <osp@andrep.de>

Author: apritzel

fel-spiflash.c

@@ -124,22 +124,7 @@ void fel_writel(feldev_handle *dev, uint32_t addr, uint32_t val);
 
 static uint32_t spi_base(feldev_handle *dev)
 {
-	soc_info_t *soc_info = dev->soc_info;
-	switch (soc_info->soc_id) {
-	case 0x1623: /* A10 */
-	case 0x1625: /* A13 */
-	case 0x1651: /* A20 */
-	case 0x1663: /* F1C100s */
-	case 0x1701: /* R40 */
-		return 0x01C05000;
-	case 0x1816: /* V536 */
-	case 0x1817: /* V831 */
-	case 0x1728: /* H6 */
-	case 0x1823: /* H616 */
-		return 0x05010000;
-	default:
-		return 0x01C68000;
-	}
+	return dev->soc_info->spi_base;
 }
 
 /*

soc_info.c

@@ -336,6 +336,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_a10_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN4I_SPI_BASE,
 		.flags        = NEEDS_L2EN,
 	},{
 		.soc_id       = 0x1625, /* Allwinner A10s, A13, R8 */
@@ -348,6 +349,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_a10_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN4I_SPI_BASE,
 		.flags        = NEEDS_L2EN,
 	},{
 		.soc_id       = 0x1651, /* Allwinner A20 */
@@ -361,6 +363,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_a10_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN4I_SPI_BASE,
 	},{
 		.soc_id       = 0x1650, /* Allwinner A23 */
 		.name         = "A23",
@@ -412,6 +415,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h3_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN6I_SPI_BASE,
 	},{
 		.soc_id       = 0x1639, /* Allwinner A80 */
 		.name         = "A80",
@@ -437,6 +441,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h3_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN4I_SPI_BASE,
 	},{
 		.soc_id       = 0x1673, /* Allwinner A83T */
 		.name         = "A83T",
@@ -467,6 +472,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h3_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN6I_SPI_BASE,
 		.flags        = NEEDS_SID_FIX,
 	},{
 		.soc_id       = 0x1681, /* Allwinner V3s */
@@ -481,6 +487,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h3_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN6I_SPI_BASE,
 	},{
 		.soc_id       = 0x1708, /* Allwinner T7 */
 		.name         = "T7",
@@ -513,6 +520,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h3_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN6I_SPI_BASE,
 	},{
 		.soc_id       = 0x1701, /* Allwinner R40 */
 		.name         = "R40",
@@ -526,6 +534,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_a10_compat,
 		.gpio_base    = SUNXI_PIO_BASE,
 		.ccu_base     = AW_CCM_BASE,
+		.spi_base     = SUN4I_SPI_BASE,
 	},{
 		.soc_id       = 0x1719, /* Allwinner A63 */
 		.name         = "A63",
@@ -559,6 +568,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h6_compat,
 		.gpio_base    = H6_PIO_BASE,
 		.ccu_base     = H6_CCM_BASE,
+		.spi_base     = H6_SPI_BASE,
 		.flags        = H6_STYLE_CLOCKS,
 	},{
 		.soc_id       = 0x1816, /* Allwinner V536 */
@@ -574,6 +584,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h6_compat,
 		.gpio_base    = H6_PIO_BASE,
 		.ccu_base     = H6_CCM_BASE,
+		.spi_base     = H6_SPI_BASE,
 		.flags        = H6_STYLE_CLOCKS,
 	},{
 		.soc_id       = 0x1817, /* Allwinner V831 */
@@ -589,6 +600,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h6_compat,
 		.gpio_base    = H6_PIO_BASE,
 		.ccu_base     = H6_CCM_BASE,
+		.spi_base     = H6_SPI_BASE,
 		.flags        = H6_STYLE_CLOCKS,
 	},{
 		.soc_id       = 0x1823, /* Allwinner H616 */
@@ -607,6 +619,7 @@ soc_info_t soc_info_table[] = {
 		.watchdog     = &wd_h6_compat,
 		.gpio_base    = H6_PIO_BASE,
 		.ccu_base     = H6_CCM_BASE,
+		.spi_base     = H6_SPI_BASE,
 		.flags        = H6_STYLE_CLOCKS,
 	},{
 		.soc_id       = 0x1851, /* Allwinner R329 */

soc_info.h

@@ -97,6 +97,9 @@ enum soc_flags {
 #define V853_PIO_BASE		0x02000000
 #define R329_PIO_BASE		0x02000400
 #define R329_CCM_BASE		0x02001000
+#define SUN4I_SPI_BASE		0x01c05000
+#define SUN6I_SPI_BASE		0x01c68000
+#define H6_SPI_BASE		0x05010000
 
 /*
  * Each SoC variant may have its own list of memory buffers to be exchanged
@@ -158,6 +161,7 @@ typedef struct {
 	sram_swap_buffers *swap_buffers;
 	uint32_t           gpio_base;
 	uint32_t           ccu_base;
+	uint32_t           spi_base;
 	uint32_t           flags;
 } soc_info_t;