From e70f261773d9b826df88e4c7e43f970291fc84aa Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Mon, 17 Mar 2025 16:29:42 +0300 Subject: [PATCH 1/4] CCU/CCM base is different on T113S --- fel-spiflash.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/fel-spiflash.c b/fel-spiflash.c index 95cab875c..63926f5ff 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -83,8 +83,8 @@ void fel_writel(feldev_handle *dev, uint32_t addr, uint32_t val); #define SUNIV_PLL6_CTL (0x01c20000 + 0x28) #define SUNIV_AHB_APB_CFG (0x01c20000 + 0x54) -#define H6_CCM_SPI0_CLK (0x03001000 + 0x940) -#define H6_CCM_SPI_BGR (0x03001000 + 0x96C) +#define H6_CCM_SPI0_CLK (ccm_base(dev) + 0x940) +#define H6_CCM_SPI_BGR (ccm_base(dev) + 0x96C) #define H6_CCM_SPI0_GATE_RESET (1 << 0 | 1 << 16) #define SUNIV_GPC_SPI0 (2) @@ -156,6 +156,18 @@ static uint32_t spi_base(feldev_handle *dev) } } +static uint32_t ccm_base(feldev_handle *dev) +{ + soc_info_t *soc_info = dev->soc_info; + switch (soc_info->soc_id) { + case 0x1859: /* D1/D1s/R528/T113-S3 */ + // CCU + return 0x02001000; + default: + return 0x03001000; + } +} + /* * Configure pin function on a GPIO port */ From ed12eb6dc9a1312df6f3afed0a7c08a3611c8854 Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Mon, 17 Mar 2025 16:32:03 +0300 Subject: [PATCH 2/4] T113S: gpio bank step is not 0x24 on T113S --- fel-spiflash.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/fel-spiflash.c b/fel-spiflash.c index 63926f5ff..372757481 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -122,7 +122,7 @@ void fel_writel(feldev_handle *dev, uint32_t addr, uint32_t val); #define CCM_SPI0_CLK_DIV_BY_6 (0x1002) #define CCM_SPI0_CLK_DIV_BY_32 (0x100f) -static uint32_t gpio_base(feldev_handle *dev) +static uint32_t gpio_base(feldev_handle *dev, int port_num) { soc_info_t *soc_info = dev->soc_info; switch (soc_info->soc_id) { @@ -130,9 +130,11 @@ static uint32_t gpio_base(feldev_handle *dev) case 0x1817: /* V831 */ case 0x1728: /* H6 */ case 0x1823: /* H616 */ - return 0x0300B000; + return 0x0300B000 + port_num * 0x24; + case 0x1859: /* D1/D1s/R528/T113-S3 */ + return 0x02000000 + port_num * 0x30; default: - return 0x01C20800; + return 0x01C20800 + port_num * 0x24; } } @@ -174,11 +176,11 @@ static uint32_t ccm_base(feldev_handle *dev) static void gpio_set_cfgpin(feldev_handle *dev, int port_num, int pin_num, int val) { - uint32_t port_base = gpio_base(dev) + port_num * 0x24; + uint32_t port_base = gpio_base(dev, port_num); uint32_t cfg_reg = port_base + 4 * (pin_num / 8); uint32_t pin_idx = pin_num % 8; uint32_t x = readl(cfg_reg); - x &= ~(0x7 << (pin_idx * 4)); + x &= ~(0xf << (pin_idx * 4)); x |= val << (pin_idx * 4); writel(x, cfg_reg); } From e1a0d4f69cc750773da4a2fe6e56b87f2e265086 Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Mon, 17 Mar 2025 16:33:01 +0300 Subject: [PATCH 3/4] T113S: SPI pinmux --- fel-spiflash.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fel-spiflash.c b/fel-spiflash.c index 372757481..42b57ecc7 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -90,6 +90,7 @@ void fel_writel(feldev_handle *dev, uint32_t addr, uint32_t val); #define SUNIV_GPC_SPI0 (2) #define SUNXI_GPC_SPI0 (3) #define SUN50I_GPC_SPI0 (4) +#define SUN8I_GPC_SPI0 (2) #define SUN4I_CTL_ENABLE (1 << 0) #define SUN4I_CTL_MASTER (1 << 1) @@ -273,6 +274,14 @@ static bool spi0_init(feldev_handle *dev) gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0); /* SPI0_CS0 */ gpio_set_cfgpin(dev, PC, 4, SUN50I_GPC_SPI0); /* SPI0_MISO */ break; + case 0x1859: /* Allwinner D1/D1s/R528/T113-S3 */ + gpio_set_cfgpin(dev, PC, 2, SUN8I_GPC_SPI0); /* SPI0_CLK */ + gpio_set_cfgpin(dev, PC, 4, SUN8I_GPC_SPI0); /* SPI0_MOSI */ + gpio_set_cfgpin(dev, PC, 3, SUN8I_GPC_SPI0); /* SPI0_CS0 */ + gpio_set_cfgpin(dev, PC, 5, SUN8I_GPC_SPI0); /* SPI0_MISO */ + gpio_set_cfgpin(dev, PC, 6, SUN8I_GPC_SPI0); /* SPI0_WP */ + gpio_set_cfgpin(dev, PC, 7, SUN8I_GPC_SPI0); /* SPI0_HOLD */ + break; default: /* Unknown/Unsupported SoC */ printf("SPI support not implemented yet for %x (%s)!\n", soc_info->soc_id, soc_info->name); From c6612c5157e78a474b5c2b2129a26b0da5b394a6 Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Mon, 17 Mar 2025 16:33:28 +0300 Subject: [PATCH 4/4] T113S: SPI0 base and SPI style --- fel-spiflash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fel-spiflash.c b/fel-spiflash.c index 42b57ecc7..bb4f125c2 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -154,6 +154,8 @@ static uint32_t spi_base(feldev_handle *dev) case 0x1728: /* H6 */ case 0x1823: /* H616 */ return 0x05010000; + case 0x1859: /* D1/D1s/R528/T113-S3 */ + return 0x04025000; default: return 0x01C68000; } @@ -207,6 +209,7 @@ static bool soc_is_h6_style(feldev_handle *dev) case 0x1817: /* V831 */ case 0x1728: /* H6 */ case 0x1823: /* H616 */ + case 0x1859: /* D1/D1s/R528/T113-S3 */ return true; default: return false;