You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Copy file name to clipboardExpand all lines: blobs/w541/README.md
+5Lines changed: 5 additions & 0 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -8,6 +8,7 @@
8
8
Coreboot on the W541 requires the following binary blobs:
9
9
10
10
-`mrc.bin` - Consists of Intel’s Memory Reference Code (MRC) and [is used to initialize the DRAM](https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html).
11
+
- Known issues with ram initilization are listed below.
11
12
-`me.bin` - Consists of Intel’s Management Engine (ME), which we modify using [me_cleaner](https://github.com/corna/me_cleaner) to remove all but the modules which are necessary for the CPU to function.
12
13
-`gbe.bin` - Consists of hardware/software configuration data for the Gigabit Ethernet (GbE) controller. Intel publishes the data structure [here](https://web.archive.org/web/20230122164346/https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/i-o-controller-hub-8-9-nvm-map-guide.pdf), and an [ImHex](https://github.com/WerWolv/ImHex) hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_lan_nvm.hexpat).
13
14
-`ifd.bin` - Consists of the Intel Flash Descriptor (IFD). Intel publishes the data structure [here](https://web.archive.org/web/20221208011432/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/io-controller-hub-8-datasheet.pdf), and an ImHex hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_flash_descriptor.hexpat).
@@ -38,3 +39,7 @@ Now, you can rebuild Heads:
38
39
```console
39
40
$ make BOARD=w541-hotp-maximized
40
41
```
42
+
43
+
# Known Issues
44
+
- Ram initialization with the MRC blob is very slow (~40s until boot splash) and so far native ram init (NRI) which was merged upstream has not been able to resolve the issue under heads. Work on HRI is tracked here: https://github.com/linuxboot/heads/pull/1923
45
+
- S3 resume from suspend has been reported as flaky on some boards (4 DIMMs with a total of 32GB ram).
Copy file name to clipboardExpand all lines: blobs/xx80/README.md
+7-4Lines changed: 7 additions & 4 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -7,9 +7,10 @@ The following blobs are needed:
7
7
*`me.bin`
8
8
*`tb.bin` (optional but recommended flashing this blob to the separate Thunderbolt SPI chip to fix a bug in the original firmware)
9
9
10
-
## me.bin: automatically extract, neuter and deguard
10
+
## me.bin: automatically extract, deactivate, partially neuter and deguard
11
11
12
-
download_clean_me.sh : Download vulnerable ME from Dell, verify checksum, extract ME, neuter ME and trim it, then apply the deguard patch and place it into me.bin
12
+
download_clean_deguard_me_pad_tb.sh : Download vulnerable ME from Dell, verify checksum, extract ME, deactivate ME and paritally neuter it, then apply the deguard patch and place it into me.bin.
13
+
For the technical details please read the documentation in the script itself, as removing modules is limited on the platform.
13
14
14
15
The ME blob dumped in this directory comes from the following link: https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe
15
16
@@ -31,7 +32,7 @@ The GBE MAC address was forged to: `00:DE:AD:C0:FF:EE MAC`
31
32
## tb.bin
32
33
33
34
This blob was extracted from https://download.lenovo.com/pccbbs/mobiles/n24th13w.exe
34
-
It is zero-padded to 1MB and should be flashed to the Thunderbolt SPI chip, which is not the same as the 16MB chip to which the heads rom is flashed. External flashing is recommended as the only way to reliably fix a bug in the original Thunderbolt software on the SPI chip. You can find a guide here: https://osresearch.net/T430-maximized-flashing/
35
+
It is zero-padded to 1MB and should be flashed to the Thunderbolt SPI chip, which is not the same as the 16MB chip to which the heads rom is flashed. External flashing is recommended as the only way to reliably fix a bug in the original Thunderbolt software on the SPI chip. You can find a guide here: https://osresearch.net/T480-maximized-flashing/
35
36
36
37
## Integrity
37
38
@@ -50,4 +51,6 @@ See the board configs `boards/t480-[hotp-]maximized/t480-[hotp-]maximized.config
50
51
# Documentation
51
52
52
53
A guide on how to flash this board (both the Heads rom and the Thunderbolt `tb.bin` blob) can be found here:
53
-
https://osresearch.net/T430-maximized-flashing/
54
+
https://osresearch.net/T480-maximized-flashing/
55
+
56
+
The upstream documentation is available here. It includes a list of known issues: https://doc.coreboot.org/mainboard/lenovo/t480.html
Copy file name to clipboardExpand all lines: boards/EOL_UNTESTED_optiplex-7010_9010-hotp-maximized/EOL_UNTESTED_optiplex-7010_9010-hotp-maximized.config
+1-1Lines changed: 1 addition & 1 deletion
Original file line number
Diff line number
Diff line change
@@ -8,7 +8,7 @@
8
8
#
9
9
# - Includes: Nitrokey/Librem Key HOTP Security dongle remote attestation (in addition to TOTP remote attestation through Qr Code)
Copy file name to clipboardExpand all lines: boards/EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized/EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized.config
+1-1Lines changed: 1 addition & 1 deletion
Original file line number
Diff line number
Diff line change
@@ -8,7 +8,7 @@
8
8
#
9
9
# - Includes: Nitrokey/Librem Key HOTP Security dongle remote attestation (in addition to TOTP remote attestation through Qr Code)
0 commit comments