boards, blobs: add TPM_GPIO_RESET CAVEATS annotations to board configs

Add '# CAVEATS: TPM_GPIO_RESET=' comment to 50 hardware board
configs. NOT_VULNERABLE for Pre-Skylake (dedicated PLTRST# pin)
and Talos II (POWER9). VULNERABLE for Skylake through Comet Lake.
VULNERABILITY UNCERTAIN for ADL-P 0x5182 (NV4x, NS50 — writes
verify, PLTRST# not confirmed on this die). NOT_APPLICABLE for
Librem 11, Mini v1, Mini v2 (CONFIG_NO_TPM=y, no TPM hardware).
NOT_VULNERABLE for MTL v540tu/v560tu (eSPI TPM, SLB 9672).

blobs: update TPM reset attack references in m900 and xx80 READMEs.
Signed-off-by: Thierry Laurion <insurgo@riseup.net>

Author: tlaurion

.opencode/claim-verification.md

@@ -0,0 +1,19 @@
+# Plan: PR #2158
+
+## Sub-tasks
+1. Extract shared functions from OEM — DONE
+2. Add reprovision flow — DONE
+3. GUI integration — DONE
+4. mount-usb.sh --pass-file — DONE
+5. Documentation — DONE
+6. Review fixes — DONE (7+ copilot rounds addressed)
+7. Final validation + review — IN PROGRESS
+
+## Done-when
+- [x] bash -n clean on all changed scripts
+- [x] No new shellcheck errors (pre-existing warnings OK)
+- [x] All PINs use --passphrase-fd 3 3< or --key-file (no argv leak)
+- [x] Temp secrets shredded on success and error paths
+- [x] OEM thin wrappers preserve original behavior
+- [x] Single signed commit
+- [ ] review.md written with no blocking findings

.opencode/plan.md

@@ -0,0 +1,192 @@
+# Final Review: `doc/tpm-gpio-vuln` branch — heads repo
+
+**Date**: 2026-07-21
+**Branch**: `doc/tpm-gpio-vuln` (55 files, +2333/-65 lines)
+**Reviewer**: Oracle
+
+---
+
+## Overall Verdict: CHANGES REQUESTED (2 blocking findings)
+
+The branch is close to ready. Two staleness issues remain in the Approaches doc
+(appendix and testing sections that weren't updated when the script's register
+computation was corrected). All other criteria pass or have minor notes.
+
+---
+
+## Blocking Findings
+
+### B1: Approaches doc Appendix A — stale SPT register computation (lines 663-666)
+
+**File**: `doc/TPM_GPIO_Reset_Approaches.md`
+**Lines**: 663-666
+
+Current text:
+```
+uses 4 DWORDS, starting at PAD_CFG_BASE. GPP_B13 is global pad 37, which is
+local index 13 within GROUP_B. DW0 = PAD_CFG_BASE + (37 * 16) = 0x400 + 0x250 = 0x650.
+Total address = 0xFD00_0650.
+```
+
+**Problems**:
+1. "4 DWORDS" is wrong — SPT uses 2 DWORDS per `skylake/gpio_defs.h:12`
+2. DW0 offset should be `0x400 + 37 * 8 = 0x528`, not `0x400 + 37 * 16 = 0x650`
+3. Address should be `0xFDAF0528` (with port shift), not `0xFD00_0650`
+
+The script itself was corrected (NUM_PAD_CFG_REGS=2, offset 0x528) but this
+appendix section was missed.
+
+**Correction**:
+```
+uses 2 DWORDS (8 bytes per `skylake/gpio_defs.h` line 12:
+`GPIO_NUM_PAD_CFG_REGS 2`). DW0 = PAD_CFG_BASE + (37 * 8)
+= 0x400 + 0x128 = 0x528. Total address = 0xFDAF0528.
+```
+
+### B2: Approaches doc SPT community testing section — stale address (line 553)
+
+**File**: `doc/TPM_GPIO_Reset_Approaches.md`
+**Line**: 553
+
+Current text:
+```
+- Register address: 0xFD00_0474 (with PCR_BASE = 0xFD000000).
+```
+
+**Problem**: `0xFD00_0474` was computed as `0x400 + (13 * 4 * 4) = 0x400 + 0xD0 = 0x4D0`
+with port 0xAF applied incorrectly (missing 0xAF << 16). The correct address is
+`0xFDAF0528` per verified offset 0x528. Also the pad is global pad 37, not 13.
+
+**Correction**:
+```
+- Register address: 0xFDAF0528 (offset 0x528 = 0x400 + 37*8, port 0xAF << 16, PCR_BASE 0xFD000000).
+```
+
+---
+
+## Non-Blocking Findings
+
+### N1: `blobs/README.md` files only partially updated
+
+**Files**: `blobs/m900/README.md`, `blobs/xx80/README.md`
+**Lines**: Pre-existing caveat sections
+
+The blobs/README.md files had "TPM reset" changed to "TPM GPIO reset" but the
+body text still says "extract FDE keys from a TPM." The board configs were
+updated to the new language ("TOTP/HOTP secret extractable, DUK with passphrase
+safe") but the blobs/README.md retained the old language. Recommend updating
+to match the board configs.
+
+### N2: Script header says ADL-P "TESTED" but mechanism "NOT confirmed working"
+
+**File**: `initrd/bin/tpm-gpio-reset-demo.sh`
+**Line**: 74-75
+
+```
+#    This method IS IMPLEMENTED here. TESTED on NV4x ADL-P: write verified,
+#    PCRs do not clear -- mechanism NOT confirmed working.
+```
+
+Slightly confusing — "IS IMPLEMENTED" suggests it works, but the rest of the
+sentence says it doesn't. The script correctly reports failure when run with
+--execute. Consider rephrasing:
+
+```
+#    Register address verified (0xFD6E07D0). Write confirmed by readback.
+#    However, PCRs do not clear after PLTRST# assertion on this PCH die.
+#    Execute mode will report this honestly.
+```
+
+### N3: Approaches doc line 553 uses "local pad index 13" for SPT
+
+**Line**: 553
+
+Says `local pad index 13` but GPP_B13 on SPT is global pad 37. The local index
+within GPP_B group IS 13 (GPP_B0=24, GPP_B13=37, 37-24=13), but the terminology
+is ambiguous. The script correctly uses `FIRST_PAD=0` and `PLTRST_PAD=37`.
+
+### N4: Vulnerability doc summary still uses "reprogrammed to GPIO mode" language
+
+**File**: `doc/TPM_GPIO_Reset_Vulnerability.md`
+**Lines**: 6-8
+
+The summary section describes the attack as "reprogrammed to GPIO mode" which
+is accurate for CNP-H but not for SPT/ADL (where the mechanism is writing to a
+PLTRST# assertion register at a fixed offset). The rest of the document correctly
+distinguishes mechanisms. Consider adding a brief qualification in the summary.
+
+### N5: per-platform feasibility says ADL-P Dasharo "Yes"
+
+**File**: `doc/TPM_GPIO_Reset_Vulnerability.md`
+**Line**: 227
+
+The "Yes" for ADL/RPL Dasharo covers NV4x/NS50 (ADL-P) which was tested and
+confirmed NOT working (PCRs don't clear despite unlocked pad). Should be split
+into ADL-P "No" and ADL-S/RPL-S "Unknown."
+
+---
+
+## Per-Criterion Assessment
+
+### 1. Factual accuracy: PASS (with B1-B2 fixes)
+- TCG spec sections: Sections 4, 12.2.3.2, 37 used correctly throughout ✅
+- Section 27.2 parent reference removed ✅
+- Section 27.2.6 retained for Unseal command (correct) ✅
+- Register addresses: corrected to verified values in script and Approaches doc table ✅
+- Platform status: verified against Dasharo/Purism forks ✅
+- SPT NUM_PAD_CFG_REGS=2 verified against coreboot ✅
+- CNP-H port 0x6B, first_pad=HDA_BCLK=107 verified ✅
+- ADL-P tested: write verified, PCRs don't clear — honestly reported ✅
+
+### 2. Per-platform consistency: PASS
+- All board configs use consistent single-line caveat format ✅
+- BOARDS_AND_TESTERS table matches board config caveats ✅
+- TPM doc per-platform table matches BOARDS_AND_TESTERS ✅
+- Script detect_platform() statuses match documentation ✅
+
+### 3. Attack mechanism clarity: PASS
+- "TPM GPIO reset" used consistently throughout (no bare "TPM reset" in new content) ✅
+- Old "TPM reset attack" language removed from board configs ✅
+- Board configs updated from verbose to concise `TPM_GPIO_RESET=VULNERABLE` format ✅
+- Legacy language only in blobs/README.md (partial update) ⚠️ N1
+
+### 4. TCG spec references: PASS
+- Sections 4, 12.2.3.2, 37 used for volatile/non-volatile guarantees ✅
+- Section 27.2.6 used only for Unseal command (correct) ✅
+- No PLTRST# attributed to TCG spec ✅
+- Attacks doc aligns with Vulnerability doc references ✅
+
+### 5. BusyBox compliance: PASS
+- No `od` usage (xxd used; comment correctly notes od is unavailable) ✅
+- `set -eo pipefail` present ✅
+- `TRACE_FUNC` used for function entry ✅
+- No `echo >/dev/console` ✅
+- `command -v` used directly (no custom has_cmd) ✅
+- `xxd -p | tr -d '\n '` correctly handles BusyBox padding ✅
+
+### 6. User-facing vs developer docs: PASS
+- TPM_GPIO_Reset_Vulnerability.md: technical, precise, cites source files ✅
+- TPM_GPIO_Reset_Approaches.md: chronicle of development, register-level detail ✅
+- BOARDS_AND_TESTERS.md: summary table with technical statuses ✅
+
+### 7. TL;DR clarity: ⚠️ MINOR
+- **T480/480s wiki pages**: First paragraph is neutral description, doesn't immediately
+  tell user they're affected. The "this platform" marker is in a table row further down.
+  Consider adding bold: **This platform is affected.**
+- **T420/T430/x230**: Heading says "Not Affected", first line says "not affected" ✅
+
+### 8. Mitigation guidance: PASS
+- "DUK with passphrase is not affected" present in all docs ✅
+- Recovery shell GPG auth mentioned as mitigation ✅
+- Per-board status table tells users which boards are safe ✅
+- Fix noted as coreboot upstream responsibility ✅
+
+---
+
+## Follow-Up (deferrable)
+
+1. Test SPT/KBP on actual hardware (T480 KBL) to confirm mechanism works
+2. Test CNP-H on actual hardware (T480s) to confirm mechanism works
+3. Investigate why PLTRST# assertion doesn't reset TPM on ADL-P (PCH routing?)
+4. Update `blobs/README.md` to match board config language
+5. Review wiki T480/T480s first paragraphs for TL;DR clarity