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Merge pull request #729 from GMM-7550/gmm7550
GMM-7550 module support
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‎README.md‎

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@@ -167,6 +167,7 @@ Some of the supported boards, see yours? Give LiteX-Boards a try!
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├── fpc_iii
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├── fpgawars_alhambra2
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├── gadgetfactory_papilio_pro
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├── gmm7550_usb3
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├── gsd_butterstick
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├── gsd_orangecrab
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├── hackaday_hadbadge

‎litex_boards/platforms/gmm7550.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2026 Anton Kuzmin <ak@gmm7550.dev>
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#
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# Based on CologneChip GateMate Evaluation Board (colognechip_gatemate_evb)
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# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board documentation/schematics:
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# https://www.gmm7550.dev/doc/module.html
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from litex.build.generic_platform import *
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from litex.build.colognechip.platform import CologneChipPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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_io = [
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# Main reference clock (100 MHz, module PLL)
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("ser_clk", 0, Pins("SER_CLK")),
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# SPI NOR Flash (FPGA configuration, MUXed with signals on P5 connector)
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("spiflash", 0,
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Subsignal("cs_n", Pins("IO_WA_A8")),
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Subsignal("clk", Pins("IO_WA_B8")),
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Subsignal("mosi", Pins("IO_WA_B7")), # D0
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Subsignal("miso", Pins("IO_WA_A7")), # D1
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Subsignal("wp", Pins("IO_WA_B6")), # D2
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Subsignal("hold", Pins("IO_WA_A6")), # D3
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("IO_WA_A8")),
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Subsignal("clk", Pins("IO_WA_B8")),
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Subsignal("dq", Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_A6")),
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),
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# UART
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("serial", 0,
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Subsignal("rx", Pins("IO_WA_B6")), # SPI D2, P5/J5 pin 31
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Subsignal("tx", Pins("IO_WA_A6")), # SPI D3, P5/J5 pin 33
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),
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# Status LEDs on the USB 3 Adapter board
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("led_red_n", 0, Pins("IO_WA_A2")), # CFG_FAILED_N, P5/J5 pin 35
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("led_green", 0, Pins("IO_WA_B2")), # CFG_DONE, P5/J5 pin 36
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# JTAG
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("jtag", 0,
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Subsignal("tck", Pins("IO_WA_A5")),
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Subsignal("tms", Pins("IO_WA_B4")),
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Subsignal("tdi", Pins("IO_WA_A4")),
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Subsignal("tdo", Pins("IO_WA_B3")),
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),
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]
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# GMM-7550 Module Connectors
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_connectors = [
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# West ------------------------
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("P1", "-", # 0
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" --- --- ", # 1 2
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"IO_WB_B1 IO_WB_B0", # 3 4
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"IO_WB_A1 IO_WB_A0", # 5 6
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" --- --- ", # 7 8
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"IO_WB_B2 IO_WB_B3", # 9 10
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"IO_WB_A2 IO_WB_A3", # 11 12
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" --- --- ", # 13 14
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"IO_WB_B4 IO_WB_B5", # 15 16
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"IO_WB_A4 IO_WB_A5", # 17 18
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" --- --- ", # 19 20
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"IO_WB_B6 IO_WB_B7", # 21 22
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"IO_WB_A6 IO_WB_A7", # 23 24
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" --- --- ", # 25 26
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"IO_WB_B8 IO_WC_B0", # 27 28
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"IO_WB_A8 IO_WC_A0", # 29 30
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"--- --- ", # 31 32
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"--- --- ", # 33 34
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"--- --- ", # 35 36
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"IO_WC_B1 IO_WC_B3", # 37 38
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"IO_WC_A1 IO_WC_A3", # 39 40
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" --- --- ", # 41 42
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"IO_WC_B2 IO_WC_B5", # 43 44
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"IO_WC_A2 IO_WC_A5", # 45 46
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" --- --- ", # 47 48
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"IO_WC_B4 IO_WC_B8", # 49 50
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"IO_WC_A4 IO_WC_A8", # 51 52
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" --- --- ", # 53 54
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"IO_WC_B6 IO_WC_B7", # 55 56
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"IO_WC_A6 IO_WC_A7", # 57 58
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" --- --- ", # 59 60
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),
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# North ------------------------
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("P2", "-", # 0
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" --- --- ", # 1 2
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"IO_NA_B2 IO_NA_B0", # 3 4
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"IO_NA_A2 IO_NA_A0", # 5 6
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" --- --- ", # 7 8
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"IO_NA_B3 IO_NA_B1", # 9 10
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"IO_NA_A3 IO_NA_A1", # 11 12
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" --- --- ", # 13 14
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"IO_NA_B5 IO_NA_B4", # 15 16
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"IO_NA_A5 IO_NA_A4", # 17 18
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" --- --- ", # 19 20
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"IO_NA_B6 IO_NA_B7", # 21 22
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"IO_NA_A6 IO_NA_A7", # 23 24
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" --- --- ", # 25 26
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"IO_NA_B8 IO_NB_B0", # 27 28
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"IO_NA_A8 IO_NB_A0", # 29 30
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"--- --- ", # 31 32
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"--- --- ", # 33 34
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"--- --- ", # 35 36
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"IO_NB_B1 IO_NB_B2", # 37 38
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"IO_NB_A1 IO_NB_A2", # 39 40
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" --- --- ", # 41 42
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"IO_NB_B3 IO_NB_B4", # 43 44
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"IO_NB_A3 IO_NB_A4", # 45 46
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" --- --- ", # 47 48
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"IO_NB_B5 IO_NB_B7", # 49 50
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"IO_NB_A5 IO_NB_A7", # 51 52
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" --- --- ", # 53 54
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"IO_NB_B6 IO_NB_B8", # 55 56
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"IO_NB_A6 IO_NB_A8", # 57 58
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" --- --- ", # 59 60
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),
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# East ------------------------
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("P3", "-", # 0
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" --- --- ", # 1 2
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"IO_EB_B7 IO_EB_B8", # 3 4
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"IO_EB_A7 IO_EB_A8", # 5 6
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" --- --- ", # 7 8
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"IO_EB_B5 IO_EB_B4", # 9 10
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"IO_EB_A5 IO_EB_A4", # 11 12
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" --- --- ", # 13 14
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"IO_EB_B6 IO_EB_B2", # 15 16
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"IO_EB_A6 IO_EB_A2", # 17 18
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" --- --- ", # 19 20
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"IO_EB_B3 IO_EB_B0", # 21 22
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"IO_EB_A3 IO_EB_A0", # 23 24
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" --- --- ", # 25 26
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"IO_EB_B1 IO_EA_B7", # 27 28
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"IO_EB_A1 IO_EA_A7", # 29 30
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"--- --- ", # 31 32
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"--- --- ", # 33 34
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"--- --- ", # 35 36
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"IO_EA_B8 IO_EA_B4", # 37 38
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"IO_EA_A8 IO_EA_A4", # 39 40
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" --- --- ", # 41 42
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"IO_EA_B6 IO_EA_B2", # 43 44
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"IO_EA_A6 IO_EA_A2", # 45 46
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" --- --- ", # 47 48
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"IO_EA_B5 IO_EA_B1", # 49 50
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"IO_EA_A5 IO_EA_A1", # 51 52
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" --- --- ", # 53 54
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"IO_EA_B3 IO_EA_B0", # 55 56
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"IO_EA_A3 IO_EA_A0", # 57 58
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" --- --- ", # 59 60
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),
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# South ------------------------
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("P4", "-", # 0
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" --- --- ", # 1 2
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"IO_SB_B8 IO_SB_B3", # 3 4
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"IO_SB_A8 IO_SB_A3", # 5 6
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" --- --- ", # 7 8
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"IO_SB_B6 IO_SB_B2", # 9 10
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"IO_SB_A6 IO_SB_A2", # 11 12
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" --- --- ", # 13 14
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"IO_SB_B5 IO_SB_B1", # 15 16
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"IO_SB_A5 IO_SB_A1", # 17 18
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" --- --- ", # 19 20
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"IO_SB_B7 IO_SB_B0", # 21 22
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"IO_SB_A7 IO_SB_A0", # 23 24
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" --- --- ", # 25 26
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"IO_SB_B4 IO_SA_B8", # 27 28
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"IO_SB_A4 IO_SA_A8", # 29 30
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"--- --- ", # 31 32
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"--- --- ", # 33 34
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"--- --- ", # 35 36
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"IO_SA_B6 IO_SA_B7", # 37 38
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"IO_SA_A6 IO_SA_A7", # 39 40
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" --- --- ", # 41 42
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"IO_SA_B4 IO_SA_B5", # 43 44
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"IO_SA_A4 IO_SA_A5", # 45 46
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" --- --- ", # 47 48
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"IO_SA_B2 IO_SA_B3", # 49 50
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"IO_SA_A2 IO_SA_A3", # 51 52
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" --- --- ", # 53 54
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"IO_SA_B1 IO_SA_B0", # 55 56
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"IO_SA_A1 IO_SA_A0", # 57 58
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" --- --- ", # 59 60
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(CologneChipPlatform):
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default_clk_name = "ser_clk"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="peppercorn"):
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CologneChipPlatform.__init__(self, "CCGM1A1", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return OpenFPGALoader(cable="dirtyJtag")
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def do_finalize(self, fragment):
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CologneChipPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
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self.default_clk_period)

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