targets: use SoC HyperRAM helper

Replace direct HyperRAM instantiation in direct-mapped targets with SoC.add_hyperram(), letting the SoC bus standard select Wishbone, AXI-Lite or AXI natively.

Keep special cached/legacy HyperRAM paths unchanged, and remove imports made redundant by the helper conversion.

Verified with py_compile on converted targets and Trenz S7 Mini gateware export for both default Wishbone and --bus-standard=axi.

Author: enjoy-digital

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -17,7 +17,6 @@
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import *
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 from litex.soc.cores.bitbang import I2CMaster
@@ -30,8 +29,6 @@
 from litedram.common import PhySettings, GeomSettings, TimingSettings
 
 from liteeth.phy import LiteEthS7PHYRGMII
-from litex.soc.cores.hyperbus import HyperRAM
-
 from litespi.modules import S25FL128S0
 from litespi.opcodes import SpiNorFlashOpCodes as Codes
 
@@ -117,8 +114,10 @@ def __init__(self, *, sys_clk_freq=100e6, iodelay_clk_freq=200e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx"))
+            self.add_hyperram(
+                origin = 0x20000000,
+                size   = 8*MEGABYTE,
+            )
 
         # SD Card ----------------------------------------------------------------------------------
         if with_sdcard:

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -13,16 +13,13 @@
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc import *
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT53E256M16D1
 from litedram.phy import lpddr4
 
 from liteeth.phy import LiteEthS7PHYRGMII
-from litex.soc.cores.hyperbus import HyperRAM
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -81,8 +78,10 @@ def __init__(self, *, sys_clk_freq=50e6, iodelay_clk_freq=200e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx"))
+            self.add_hyperram(
+                origin = 0x20000000,
+                size   = 8*MEGABYTE,
+            )
 
         # SD Card ----------------------------------------------------------------------------------
         if with_sdcard:

litex_boards/targets/brisbaneSilicon_brs_100_gw1nr9.py

@@ -19,8 +19,6 @@
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
-from litex.soc.cores.hyperbus import HyperRAM
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -16,8 +16,6 @@
 
 from litex_boards.platforms import lattice_crosslink_nx_vip
 
-from litex.soc.cores.hyperbus import HyperRAM
-
 from litex.soc.cores.ram import NXLRAM
 from litex.build.generic_platform import *
 
@@ -83,9 +81,11 @@ def __init__(self, sys_clk_freq=75e6, toolchain="radiant",
         else:
             # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
             size = 8 * MEGABYTE
-            hr_pads = platform.request("hyperram", int(hyperram))
-            self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"], size=size, mode="rwx"))
+            self.add_hyperram(
+                region_name = "sram",
+                number      = int(hyperram),
+                size        = size,
+            )
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

litex_boards/targets/sipeed_tang_nano_4k.py

@@ -19,8 +19,6 @@
 from litex.soc.cores.led import LedChaser
 from litex.soc.cores.video import *
 
-from litex.soc.cores.hyperbus import HyperRAM
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(LiteXModule):
@@ -123,8 +121,12 @@ def __init__(self):
             hyperram_pads = HyperRAMPads()
             self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
             self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
-            self.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8 * MEGABYTE, mode="rwx"))
+            self.add_hyperram(
+                pads        = hyperram_pads,
+                region_name = "main_ram",
+                origin      = 0x40000000,
+                size        = 8*MEGABYTE,
+            )
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:

litex_boards/targets/trenz_c10lpek.py

@@ -13,8 +13,6 @@
 
 from litex_boards.platforms import trenz_c10lpek
 
-from litex.soc.cores.hyperbus import HyperRAM
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.soc import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
@@ -54,12 +52,10 @@ def __init__(self, sys_clk_freq=50e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(
+            self.add_hyperram(
                 origin = 0x20000000,
                 size   = 8*MEGABYTE,
-                mode   = "rwx",
-            ))
+            )
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:

litex_boards/targets/trenz_c10lprefkit.py

@@ -16,7 +16,6 @@
 
 from litex.soc.cores.clock import Cyclone10LPPLL
 from litex.soc.integration.soc import *
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
@@ -25,7 +24,6 @@
 
 from liteeth.phy.mii import LiteEthPHYMII
 
-from litex.soc.cores.hyperbus import HyperRAM
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -75,8 +73,7 @@ def __init__(self, sys_clk_freq=50e6,
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs)
 
         # HyperRam ---------------------------------------------------------------------------------
-        self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-        self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx"))
+        self.add_hyperram(size=8*MEGABYTE)
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:

litex_boards/targets/trenz_cr00010.py

@@ -14,8 +14,6 @@
 from litex_boards.platforms import trenz_cr00010
 
 from litex.soc.cores.clock import CycloneVPLL
-from litex.soc.cores.hyperbus import HyperRAM
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.soc import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
@@ -68,12 +66,10 @@ def __init__(self, sys_clk_freq=50e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(
+            self.add_hyperram(
                 origin = 0x30000000,
                 size   = 8*MEGABYTE,
-                mode   = "rwx",
-            ))
+            )
 
         # SPI Flash --------------------------------------------------------------------------------
         if with_spi_flash:

litex_boards/targets/trenz_mega65.py

@@ -14,10 +14,8 @@
 from litex_boards.platforms import trenz_mega65
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.soc import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.hyperbus import HyperRAM
 from litex.soc.cores.led import LedChaser
 
 # CRG ----------------------------------------------------------------------------------------------
@@ -58,12 +56,10 @@ def __init__(self, sys_clk_freq=100e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(
+            self.add_hyperram(
                 origin = 0x20000000,
                 size   = 8*MEGABYTE,
-                mode   = "rwx",
-            ))
+            )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------
         if with_ethernet or with_etherbone:

litex_boards/targets/trenz_s7mini.py

@@ -14,10 +14,8 @@
 from litex_boards.platforms import trenz_s7mini
 
 from litex.soc.cores.clock import *
-from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.soc import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.hyperbus import HyperRAM
 from litex.soc.cores.led import LedChaser
 
 # CRG ----------------------------------------------------------------------------------------------
@@ -51,12 +49,10 @@ def __init__(self, sys_clk_freq=100e6,
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
-            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(
+            self.add_hyperram(
                 origin = 0x20000000,
                 size   = 8*MEGABYTE,
-                mode   = "rwx",
-            ))
+            )
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser: