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Merge pull request #678 from amhagan/AX7203
alinx_ax7203: Add AX7203 FPGA development board
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‎README.md‎

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@@ -100,6 +100,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── aliexpress_xc7k70t
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├── alinx_ax7010
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├── alinx_ax7020
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├── alinx_ax7203
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├── alinx_axu2cga
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├── analog_pocket
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├── antmicro_artix_dc_scm

‎litex_boards/platforms/alinx_ax7203.py‎

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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Aaron Hagan <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# The AX7203 FPGA development board equipped with the AMD Artix 7 series device.
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# https://en.alinx.com/Product/FPGA-Development-Boards/Artix-7/AX7203.html
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import subprocess
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("R4"), IOStandard("DIFF_SSTL15")),
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Subsignal("n", Pins("T4"), IOStandard("DIFF_SSTL15")),
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),
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("cpu_reset_n", 0, Pins("T6"), IOStandard("LVCMOS15")),
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("clk148p5", 0,
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Subsignal("p", Pins("F6"), IOStandard("LVCMOS33")),
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Subsignal("n", Pins("E6"), IOStandard("LVCMOS33"))
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),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("N15"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("P20"), IOStandard("LVCMOS33")),
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),
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# PCIe x4
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("J20"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F10")),
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Subsignal("clk_n", Pins("E10")),
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Subsignal("rx_p", Pins("D11 B8 B10 D9")),
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Subsignal("rx_n", Pins("C11 A8 A10 C9")),
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Subsignal("tx_p", Pins("D5 B4 B6 D7")),
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Subsignal("tx_n", Pins("C5 A4 A6 C7"))
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),
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# Leds
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("user_led", 0, Pins("B13"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("C13"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("D14"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("D15"), IOStandard("LVCMOS18")),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins("AA4 AB2 AA5 AB5 AB1 U3 W1 T1 V2 U2 Y1 W2 Y2 U1 V3"), IOStandard("SSTL15")),
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Subsignal("ba", Pins("AA3 Y3 Y4"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("V4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("W4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AA1"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("D2 G2 M2 M5"), IOStandard("SSTL15")),
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Subsignal("dq", Pins("C2 G1 A1 F3 B2 F1 B1 E2",
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"H3 G3 H2 H5 J1 J5 K1 H4",
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"L4 M3 L3 J6 K3 K6 J4 L5",
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"P1 N4 R1 N2 M6 N5 P6 P2"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("E1 K2 M1 P5"), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_n", Pins("D1 J2 L1 P4"), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("T5"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("U5"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("W6"), IOStandard("LVCMOS15")),
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Subsignal("cs_n", Pins("AB3"), IOStandard("SSTL15")), # Fix me
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Misc("SLEW=FAST"),
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),
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# SPIFlash
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("flash_cs_n", 0, Pins("T19"), IOStandard("LVCMOS33")),
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("flash", 0,
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("wp", Pins("P21")),
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Subsignal("hold", Pins("R21")),
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IOStandard("LVCMOS33"),
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)
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self):
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Xilinx7SeriesPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
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"set_property CFGBVS VCCO [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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]
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self.toolchain.additional_commands = [
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# Non-Multiboot SPI-Flash bitstream generation.
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin",
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# Multiboot SPI-Flash Operational bitstream generation.
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"set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]",
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"write_bitstream -force {build_name}_operational.bit ",
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_operational.bit\" -file {build_name}_operational.bin",
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# Multiboot SPI-Flash Fallback bitstream generation.
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"set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]",
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"write_bitstream -force {build_name}_fallback.bit ",
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_fallback.bit\" -file {build_name}_fallback.bin"
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]
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def detect_ftdi_chip(self):
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lsusb_log = subprocess.run(['lsusb'], capture_output=True, text=True)
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for ftdi_chip in ["ft232", "ft2232", "ft4232"]:
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if f"Future Technology Devices International, Ltd {ftdi_chip.upper()}" in lsusb_log.stdout:
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return ftdi_chip
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return None
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def create_programmer(self, name="openfpgaloader"):
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ftdi_chip = self.detect_ftdi_chip()
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return OpenFPGALoader(cable=ftdi_chip, fpga_part=f"xc7a200tfbg484", freq=10e6)
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)

‎litex_boards/targets/alinx_ax7203.py‎

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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2025 Aaron Hagan <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import alinx_ax7203
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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from litedram.modules import MT41J256M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_dqs = ClockDomain()
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self.cd_idelay = ClockDomain()
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# Clk.
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clk200 = platform.request("clk200")
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# Main PLL.
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self.pll = pll = S7PLL(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# IDELAY Ctrl.
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self,
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sys_clk_freq = int(200e6),
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with_led_chaser = True,
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with_pcie = False,
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**kwargs):
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platform = alinx_ax7203.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ALINX AX7203", **kwargs)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J256M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64)
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platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
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# ICAP (For FPGA reload over PCIe).
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from litex.soc.cores.icap import ICAP
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self.icap = ICAP()
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self.icap.add_reload()
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self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# Flash (For SPIFlash update over PCIe).
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.spi_flash import S7SPIFlash
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self.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
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self.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=alinx_ax7203.Platform, description="LiteX SoC on ALINX AX7203.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
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parser.add_target_argument("--driver", action="store_true", help="Generate drivers.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_led_chaser = True,
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with_pcie = args.with_pcie,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()

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