platforms: fix Kintex-7 Base C speed grade

Use the documented XC7K325TFFG676-2 part and match the target PLL speed grade to the board device.

Source: public Kintex-7 Base C bring-up notes (https://blog.ojioji.ikeojihouse.com/entry/20250216/1739633706).

Author: enjoy-digital

litex_boards/platforms/bochenjingxin_kintex7_basec.py

@@ -52,7 +52,7 @@ class Platform(Xilinx7SeriesPlatform):
     default_clk_period = 1e9/50e6
 
     def __init__(self, toolchain="vivado"):
-        device = "xc7k325tffg676-1" # FIXME: Should be xc7k325tffg676-2
+        device = "xc7k325tffg676-2"
         Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
 
     def create_programmer(self):

litex_boards/targets/bochenjingxin_kintex7_basec.py

@@ -31,7 +31,7 @@ def __init__(self, platform, sys_clk_freq):
         rst_n = platform.request("cpu_reset_n")
 
         # PLL.
-        self.pll  = pll = S7PLL(speedgrade=-1)
+        self.pll  = pll = S7PLL(speedgrade=-2)
         self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)